EECS 140
EECS 141 honors section
4 credit hours
An introductory course in digital logic circuits covering number representation, digital codes, Boolean Algebra, combinatorial logic design, sequential logic design, and programmable logic devices.
MATH 121 (Calculus I)
EECS 140 and 141 meet on the Lawrence campus during the weekdays (MWF or TR). Laboratory sections meet in the Eaton 2010 Digital Laboratory at various times during the week. Supplementary instruction sessions meet on weekdays or Sat. See the appropriate course offering page for the details of a particular semester.
All email correspondence to me regarding this class must be
addressed
To: James P.G. Sterbenz <jpgs@eecs.ku.edu> with a Subject: beginning EECS140 -. Nonconforming email is likely to be misfiltered and not be read.
Detailed information about individual offerings of this course will be located on the following pages, including schedule and reading assignments.
Further information, including homework and laboratory assignments (common to all 140 sections) is located on the EECS 140 wiki.
Generic course information are located this page below.
These textbooks and the corresponding required readings in the table are essential for success in this course. Students are responsible for knowing all of this material regardless of whether or not explicitly covered in lectures.
Stephen Brown and Zvonko Vranesic,
Fundamentals of Digital Logic with VHDL Design, 3rd edition
McGraw-Hill, 2009
Digital Logic Pocket Data Book,
Texas Instruments,
SCYD013A,
2004
Peter J. Ashenden,
The Student's
Guide to VHDL,
Morgan Kaufmann, 1998
Introduction to VHDL used in subsequent computer architecture courses, in particular EECS 443.
These books have been used in previous offerings of EECS 140 are are listed here for reference.
Peter J. Ashenden,
Digital Logic Design:
An Embedded Systems Approach using VHDL,
Morgan Kaufmann, 2008
Enoch O. Hwang,
Digital Logic
and Microprocessor Design with VHDL,
Thomson, 2006
Peter J. Ashenden,
The Designer's Guide
to VHDL, 2nd edition,
Morgan Kaufmann, 2002
Comprehensive coverage of VHDL; more advanced than The Student's Guide.
Half-size logic design template (ANSI Y32.14, IEEE 91a, or MIL-STD-806C
compliant).
All logic diagrams drawn for homework and exams must be done with the aid of a logic design template and straight edge. Hand-sketched gates and blocks are not acceptable. Homework and lab assignments are expected to be neatly prepared. Assignments, labs, and exam questions not meeting these requirements will receive a grade of zero on the corresponding sections.
This course will be graded using a the ranges in the following Grade Scale Table. It is possible that the grade distribution will be such that the numerical values will shift slightly downward, i.e. a score in the left column will result in a grade of at least the letter in the right column.
The relative contribution of course assignments to the overall grade is given in the Grade Weight table.
|
|
All exams and quizzes will be closed book and closed notes. The use of all electronic devices is prohibited during exam periods. You must read the undergraduate course exam information and the exam section of the academic integrity Web pages.
Short pop quizzes may be occasionally given if deemed necessary. Example motivations include a pop quiz at the beginning of the class to encourage prompt arrival, or to guage student understanding of the material in between exams.
All homework and laboratory assignments must be individually prepared. You must read the undergraduate homework submission guidelines and the homework section of the academic integrity Web pages.
Navigation: Up: courses – Top: James P.G. Sterbenz
Last updated 6 October 2008 –
Valid XHTML 1.1 –
Lynx inspected –
W3C AAA Conformance
©2006–2008 James P.G. Sterbenz
<jpgs@eecs.ku.edu>