*Dwidth 4.000
*	Input nodes:

j N1     vdd
j N2     vss
j N3     out
j N4     in

*	Internal nodes:


*   Transistors: ( S     D     G )

tp (2.000,8.000) tp-1    N1    N3    N4   
tn (2.000,4.000) tn-2    N2    N3    N4   

*	Capacitors:

c N4 0.043000
c N3 0.040000