From: [email-masked] (Ron Cormier)
Date: Mon, 22 Jun 92 15:15:35 PDT

Dr. Evans,

Here is the files that we used at WSU. Hopefully they are good. The 
extractions simulate reasonably and digital circuits also have
simulated ok.  

Ron

****PWELL****
//
//  Master Rules File.
//

PRECISION 100
UNIT LENGTH 1E-6

DRC_0 = EXTENT
BULK = SIZE DRC_0 BY 1.0

LAYER PWELL 41
LAYER ACTIVE 43
LAYER PSEL 44
LAYER NSEL 45
LAYER POLY 46
LAYER CONT2POLY 47
LAYER CONT2ACTIVE 48
LAYER METAL1 49
LAYER VIA 50
LAYER METAL2 51
LAYER CONT2POLY2 55
LAYER POLY2 56
LAYER OVERGLASS 52

NSUB    = BULK NOT PWELL
PDIFF   = ACTIVE AND PSEL
NDIFF   = ACTIVE AND NSEL
PDIFFOW = PDIFF NOT PWELL
NDIFFIW = PWELL AND NDIFF
NGATE   = POLY AND NDIFFIW
PGATE   = PDIFFOW AND POLY
GATES   = NGATE AND PGATE
NSRCDRN = NDIFFIW NOT NGATE
PSRCDRN = PDIFFOW NOT PGATE
PWTIE   = PDIFF AND PWELL
NSUBTIE = NDIFF NOT PWELL
CAP	= POLY AND POLY2

// Direct ICtrace Rules

CONNECT METAL1 METAL2 BY VIA		direct
CONNECT METAL1 POLY BY CONT2POLY	direct
CONNECT METAL1 POLY2 BY CONT2POLY2	direct

// Mask ICtrace Rules

CONNECT METAL1 NSRCDRN PSRCDRN PWTIE NSUBTIE ACTIVE NDIFF PDIFF BY CONT2ACTIVE	mask
CONNECT METAL1 POLY BY CONT2POLY					mask
CONNECT METAL1 METAL2 BY VIA						mask
CONNECT PWTIE PWELL							mask
CONNECT NSUBTIE NSUB							mask
CONNECT METAL1 POLY2 BY CONT2POLY2					mask

//
// ICtrace Device Definitions
//
// The following computes the "length" and "width" of P and N transistors and adjusts for
// 2.0u technology!
//
DEVICE MP(cmosp) PGATE POLY(g) PSRCDRN(s) PSRCDRN(d) NSUB(b)
[
  prop w, l, as, ad, ps, pd
  as = area(s)
  ad = area(d)
  ps = perim(s)
  pd = perim(d)
  w = ( perim_co(pgate,s) + perim_co(pgate,d) ) * 0.5
  l = ( perim(pgate) -  perim_co(pgate,s) - perim_in(pgate,s) - perim_co(pgate,d) - perim_in(pgate,d) ) * 0.5
]

DEVICE MN(cmosn) NGATE POLY(g) NSRCDRN(s) NSRCDRN(d) PWELL(b)
[  
   prop w, l, as, ad, ps, pd
   as = area(s)
   ad = area(d)
   ps = perim(s)
   pd = perim(d)
   w = ( perim_co(ngate,s) + perim_co(ngate,d) ) * 0.5
   l = ( perim(ngate) -  perim_co(ngate,s) - perim_in(ngate,s) - perim_co(ngate,d) - perim_in(ngate,d) ) * 0.5
]

DEVICE C CAP POLY POLY2 (POS NEG)

//
// Direct ICextract Rule Definitions
//

//
// Mask ICextract Rule Definitions
//

capacitance order     POLY POLY2 METAL1 METAL2                      mask

capacitance intrinsic METAL2 [.00005 .000005]                 mask
capacitance nearbody  METAL2 [.00005 5]                       mask
resistance  sheet     METAL2 [.05 0]                          mask

capacitance intrinsic METAL1 [.00005 .000005]                 mask
capacitance nearbody  METAL1 [.00005 5]                       mask
resistance  sheet     METAL1 [.07 0]                          mask

capacitance intrinsic POLY [.00005 .000005]                   mask
capacitance nearbody  POLY [.00005 10]                        mask
resistance  sheet     POLY [25 0]                             mask

resistance  sheet     POLY2 [30 0]                            mask
resistance  sheet     PDIFF [75 0]                            mask
resistance  sheet     NDIFF [20 0]                            mask

resistance connection METAL1 PDIFF [35 0]                     mask
resistance connection METAL1 NDIFF [45 0]                     mask
resistance connection METAL1 POLY [30 0]                      mask
resistance connection METAL1 POLY2 [30 0]                     mask
resistance connection METAL1 METAL2 [.4 0]                    mask

capacitance crossover METAL2 METAL1  [.000034 0 0]   mask
capacitance crossover METAL1 POLY    [.000037 0 0]   mask
capacitance crossover METAL2 POLY    [.000017 0 0]   mask 
capacitance crossover POLY POLY2     [.00050 0 0]    mask 

//
// ICrules Rule Definitions
//
subcont = EXT cont2active (active) < 2 ABUT == 0 OVERLAP OPPOSITE
wellcont = EXT cont2active (active) < 2 ABUT == 0 OVERLAP OPPOSITE

bad_active_area { @ Active area must be covered by a select
              x = active NOT psel
              x NOT nsel
}
bad_contact_poly { @ Contact to poly must be inside poly
                   cont2poly NOT INSIDE poly
}
bad_contact_active { @ Contact to active must be inside active
                   cont2active NOT INSIDE active
}
bad_pgate { @ P-type gate must not be in pwell
            pgate and pwell
}
psel_nsel { @ Overlap of N+ and P+ not allowed
            AND psel nsel
}
DRC1_1 { @ P-Well width = 10L
         INT pwell < 10 OPPOSITE
}
DRC1_2 { @ P-well spacing (different potential) = 9L
         EXT pwell < 9 NOT CONNECTED OPPOSITE
}
DRC1_3 { @ P-well spacing (same potential) = 0L or 6L
         EXT pwell < 6 CONNECTED OPPOSITE
}
DRC2_1 { @ Active area width = 3L
         INT active < 3 OPPOSITE
}
DRC2_2 { @ Active area spacing = 3L
         EXT active < 3 OPPOSITE
}
DRC2_3 { @ P-well overlap of P+ active area = 3L
         ENC pdiff pwell < 3 ABUT == 0 OVERLAP OPPOSITE
}
DRC2_4 { @ P-well overlap of N+ active area = 5L
         ENC ndiff pwell < 5 ABUT == 0 OVERLAP OPPOSITE
}
DRC3_1 { @ Poly width = 2L
         INT poly < 2 OPPOSITE
}
DRC3_2 { @ Poly spacing = 2L
         EXT poly < 2 OPPOSITE
}
DRC3_3 { @ Gate poly overlap of active = 2L
         pgate TOUCH psrcdrn == 1
         ngate TOUCH nsrcdrn == 1
         ENC active poly < 2 ABUT == 0 OPPOSITE
}
DRC3_4 { @ Active overlap of gate poly = 3L
         ENC poly active < 3 ABUT == 0 OPPOSITE
}
DRC3_5 { @ Field poly to active = 1L
         EXT poly active < 1 OPPOSITE ABUT == 0
}
DRC4_1_p { @ P+ select overlap of channel to gate poly = 3L
           x = poly INSIDE EDGE active
           ENC x pdiff < 3 ABUT == 0 OPPOSITE
}
DRC4_1_n { @ N+ select overlap of channel to gate poly = 3L
           x = poly INSIDE EDGE active
           ENC x ndiff < 3 ABUT == 0 OPPOSITE
}
DRC4_2_n { @ N+ select overlap of active = 2L
           x = cont2active INSIDE active
           y = active OUTSIDE x
           ENC y nsel < 2 ABUT == 0 OVERLAP OPPOSITE
}
DRC4_2_p { @ P+ select overlap of active = 2L
           x = cont2active INSIDE active
           y = active OUTSIDE x
           ENC y psel < 2 ABUT == 0 OVERLAP OPPOSITE
}
DRC4_3_n { @ N+ select overlap of contact to substrate = 1L
           ENC subcont nsel < 1 ABUT == 0 OPPOSITE
}
DRC4_3_p { @ P+ select overlap of contact to well = 1L
           ENC wellcont psel < 1 ABUT == 0 OPPOSITE
}
DRC4_4_n_width { @ N+ select width = 2L
                 INT nsel < 2
}
DRC4_4_n_space { @ N+ select space = 2L
                 EXT nsel < 2
}
DRC4_4_p_width { @ P+ select width = 2L
                 INT psel < 2
}
DRC4_4_p_space { @ P+ select space = 2L
                 EXT psel < 2
}
DRC5A_1 { @ Contact to poly size exactly 2L X 2L
          NOT RECTANGLE cont2poly == 2 BY == 2
}
DRC5A_2 { @ Poly overlap for contact = 1L
          @ 1L due to Rule 5B.2 (denser contacts)
          ENC cont2poly poly < 1 ABUT == 0 OVERLAP
}
DRC5A_3 { @ Contact to poly spacing = 2L
          EXT cont2poly < 2 SINGULAR
}
DRC6A_1 { @ Contact to active exactly 2L X 2L
          NOT RECTANGLE cont2active == 2 BY == 2
}
DRC6A_2 { @ Active overlap for contact = 1L
          @ 1L due to Rule 6B.2 (denser contacts)
          ENC cont2active active < 1 ABUT == 0 OVERLAP
}
DRC6A_3 { @ Contact to active spacing = 2L
          EXT cont2active < 2 SINGULAR
}
DRC6A_4 { @ Contact to active space to gate = 2L
          EXT cont2active gates < 2 ABUT == 0 REGION
}
DRC7_1 { @ Metal1 width = 3L
         INT metal1 < 3
}
DRC7_2 { @ Metal1 spacing = 3L
         EXT metal1 < 3
}
DRC7_3 { @ Metal1 overlap of contact to poly = 1L
         ENC cont2poly metal1 < 1 ABUT == 0 REGION
}
DRC7_4 { @ Metal1 overlap of contact to active = 1L
         ENC cont2active metal1 < 1 ABUT == 0 REGION
}
DRC8_1 { @ Via size exactly 2L X 2L
         NOT RECTANGLE via == 2 BY == 2
}
DRC8_2 { @ Via spacing = 3L
         EXT via < 3 SINGULAR
}
DRC8_3 { @ Via overlap by metal1 = 1L
         ENC via metal1 < 1 ABUT == 0 REGION
}
DRC8_4 { @ Via space to poly or active edge = 2L
         EXT via active < 2 ABUT == 0 OVERLAP
         ENC via active < 2 ABUT == 0
         EXT via poly < 2 ABUT == 0 OVERLAP
         ENC via poly < 2 ABUT == 0
}
DRC8_5 { @ Via spacing to contact = 2L
         EXT via cont2poly < 2 ABUT == 0 SINGULAR REGION
         EXT via cont2active < 2 ABUT == 0 SINGULAR REGION
}
DRC9_1 { @ Metal2 width = 3L
         INT metal2 < 3
}
DRC9_2 { @ Metal2 spacing = 4L
         EXT metal2 < 4
}
DRC9_3 { @ Metal2 overlap of via = 1L
         ENC via metal2 < 1 ABUT == 0 REGION
}

***NWELL*****

//
//  Master Rules File.
//

PRECISION 100
UNIT LENGTH 1E-6

DRC_0 = EXTENT
BULK = SIZE DRC_0 BY 1.0

LAYER NWELL 42
LAYER ACTIVE 43
LAYER PSEL 44
LAYER NSEL 45
LAYER POLY 46
LAYER CONT2POLY 47
LAYER CONT2ACTIVE 48
LAYER METAL1 49
LAYER VIA 50
LAYER METAL2 51
LAYER CONT2POLY2 55
LAYER POLY2 56
LAYER OVERGLASS 52

PSUB    = BULK NOT NWELL
PDIFF   = ACTIVE AND PSEL
NDIFF   = ACTIVE AND NSEL
NDIFFOW = NDIFF NOT NWELL
PDIFFIW = NWELL AND PDIFF
NGATE  = POLY AND NDIFFOW
PGATE  = PDIFFIW AND POLY
GATES   = NGATE AND PGATE
NSRCDRN = NDIFFOW NOT NGATE
PSRCDRN = PDIFFIW NOT PGATE
NWTIE   = NDIFF AND NWELL
PSUBTIE = PDIFF NOT NWELL
CAP	= POLY AND POLY2

// Direct ICtrace Rules

CONNECT METAL1 METAL2 BY VIA		direct
CONNECT METAL1 POLY BY CONT2POLY	direct
CONNECT METAL1 POLY2 BY CONT2POLY2	direct

// Mask ICtrace Rules

CONNECT METAL1 NSRCDRN PSRCDRN NWTIE PSUBTIE ACTIVE PDIFF NDIFF BY CONT2ACTIVE	mask
CONNECT METAL1 POLY BY CONT2POLY                                        mask
CONNECT METAL1 METAL2 BY VIA						mask
CONNECT NWTIE NWELL							mask
CONNECT PSUBTIE PSUB							mask
CONNECT METAL1 POLY2 BY CONT2POLY2					mask

//
// ICtrace Device Definitions
//
// The following computes the "length" and "width" of P and N transistors and adjusts for
// 2.0u technology!
//
DEVICE MP(cmosp) PGATE POLY(g) PSRCDRN(s) PSRCDRN(d) NWELL(b)
[
  prop w, l, as, ad, ps, pd
  as = area(s)
  ad = area(d)
  ps = perim(s)
  pd = perim(d)
  w = ( perim_co(pgate,s) + perim_co(pgate,d) ) * 0.5
  l = ( perim(pgate) -  perim_co(pgate,s) - perim_in(pgate,s) - perim_co(pgate,d) - perim_in(pgate,d) ) * 0.5
]

DEVICE MN(cmosn) NGATE POLY(g) NSRCDRN(s) NSRCDRN(d) PSUB(b)
[  
   prop w, l, as, ad, ps, pd
   as = area(s)
   ad = area(d)
   ps = perim(s)
   pd = perim(d)
   w = ( perim_co(ngate,s) + perim_co(ngate,d) ) * 0.5
   l = ( perim(ngate) -  perim_co(ngate,s) - perim_in(ngate,s) - perim_co(ngate,d) - perim_in(ngate,d) ) * 0.5
]

DEVICE C CAP POLY POLY2 (POS NEG)

//
// Direct ICextract Rule Definitions
//

//
// Mask ICextract Rule Definitions
//

capacitance order     POLY POLY2 METAL1 METAL2         mask

capacitance intrinsic METAL2 [.00005 .000005]                 mask
capacitance nearbody  METAL2 [.00005 5]                       mask
resistance  sheet     METAL2 [.04 0]                          mask

capacitance intrinsic METAL1 [.00005 .000005]                 mask
capacitance nearbody  METAL1 [.00005 5]                       mask
resistance  sheet     METAL1 [.07 0]                          mask

capacitance intrinsic POLY [.00005 .000005]                   mask
capacitance nearbody  POLY [.00005 10]                        mask
resistance  sheet     POLY [26 0]                             mask

resistance  sheet     POLY2 [28 0]                            mask
resistance  sheet     PDIFF [57 0]                            mask
resistance  sheet     NDIFF [28 0]                            mask

resistance connection METAL1 PDIFF [35 0]                     mask
resistance connection METAL1 NDIFF [20 0]                     mask
resistance connection METAL1 POLY [20 0]                      mask
resistance connection METAL1 POLY2 [20 0]                     mask
resistance connection METAL1 METAL2 [.4 0]                    mask

capacitance crossover METAL2 METAL1  [.000044 0 0]   mask
capacitance crossover METAL1 POLY    [.000047 0 0]   mask
capacitance crossover METAL2 POLY    [.000022 0 0]   mask 
capacitance crossover POLY POLY2     [.00055 0 0]    mask 

//
// ICrules Rule Definitions
//
subcont = EXT cont2active (active) < 2 ABUT == 0 OVERLAP OPPOSITE
wellcont = EXT cont2active (active) < 2 ABUT == 0 OVERLAP OPPOSITE

bad_active_area { @ Active area must be covered by a select
              x = active NOT psel
              x NOT nsel
}
bad_contact_poly { @ Contact to poly must be inside poly
                   cont2poly NOT INSIDE poly
}
bad_contact_active { @ Contact to active must be inside active
                   cont2active NOT INSIDE active
}
bad_ngate { @ N-type gate must not be in nwell
            ngate and nwell
}
psel_nsel { @ Overlap of N+ and P+ not allowed
            AND psel nsel
}
DRC1_1 { @ N-Well width = 10L
         INT nwell < 10 OPPOSITE
}
DRC1_2 { @ N-well spacing (different potential) = 9L
         EXT nwell < 9 NOT CONNECTED OPPOSITE
}
DRC1_3 { @ N-well spacing (same potential) = 0L or 6L
         EXT nwell < 6 CONNECTED OPPOSITE
}
DRC2_1 { @ Active area width = 3L
         INT active < 3 OPPOSITE
}
DRC2_2 { @ Active area spacing = 3L
         EXT active < 3 OPPOSITE
}
DRC2_3 { @ N-well overlap of P+ active area = 5L
         ENC pdiff nwell < 5 ABUT == 0 OVERLAP OPPOSITE
}
DRC2_4 { @ N-well overlap of N+ active area = 3L
         ENC ndiff nwell < 3 ABUT == 0 OVERLAP OPPOSITE
}
DRC3_1 { @ Poly width = 2L
         INT poly < 2 OPPOSITE
}
DRC3_2 { @ Poly spacing = 2L
         EXT poly < 2 OPPOSITE
}
DRC3_3 { @ Gate poly overlap of active = 2L
         pgate TOUCH psrcdrn == 1
         ngate TOUCH nsrcdrn == 1
         ENC active poly < 2 ABUT == 0 OPPOSITE
}
DRC3_4 { @ Active overlap of gate poly = 3L
         ENC poly active < 3 ABUT == 0 OPPOSITE
}
DRC3_5 { @ Field poly to active = 1L
         EXT poly active < 1 OPPOSITE ABUT == 0
}
DRC4_1_p { @ P+ select overlap of channel to gate poly = 3L
           x = poly INSIDE EDGE active
           ENC x pdiff < 3 ABUT == 0 OPPOSITE
}
DRC4_1_n { @ N+ select overlap of channel to gate poly = 3L
           x = poly INSIDE EDGE active
           ENC x ndiff < 3 ABUT == 0 OPPOSITE
}
DRC4_2_n { @ N+ select overlap of active = 2L
           x = cont2active INSIDE active
           y = active OUTSIDE x
           ENC y nsel < 2 ABUT == 0 OVERLAP OPPOSITE
}
DRC4_2_p { @ P+ select overlap of active = 2L
           x = cont2active INSIDE active
           y = active OUTSIDE x
           ENC y psel < 2 ABUT == 0 OVERLAP OPPOSITE
}
DRC4_3_p { @ P+ select overlap of contact to substrate = 1L
           ENC subcont psel < 1 ABUT == 0 OPPOSITE
}
DRC4_3_n { @ N+ select overlap of contact to well = 1L
           ENC wellcont nsel < 1 ABUT == 0 OPPOSITE
}
DRC4_4_n_width { @ N+ select width = 2L
                 INT nsel < 2
}
DRC4_4_n_space { @ N+ select space = 2L
                 EXT nsel < 2
}
DRC4_4_p_width { @ P+ select width = 2L
                 INT psel < 2
}
DRC4_4_p_space { @ P+ select space = 2L
                 EXT psel < 2
}
DRC5A_1 { @ Contact to poly size exactly 2L X 2L
          NOT RECTANGLE cont2poly == 2 BY == 2
}
DRC5A_2 { @ Poly overlap for contact = 1L
          @ 1L due to Rule 5B.2 (denser contacts)
          ENC cont2poly poly < 1 ABUT == 0 OVERLAP
}
DRC5A_3 { @ Contact to poly spacing = 2L
          EXT cont2poly < 2 SINGULAR
}
DRC6A_1 { @ Contact to active exactly 2L X 2L
          NOT RECTANGLE cont2active == 2 BY == 2
}
DRC6A_2 { @ Active overlap for contact = 1L
          @ 1L due to Rule 6B.2 (denser contacts)
          ENC cont2active active < 1 ABUT == 0 OVERLAP
}
DRC6A_3 { @ Contact to active spacing = 2L
          EXT cont2active < 2 SINGULAR
}
DRC6A_4 { @ Contact to active space to gate = 2L
          EXT cont2active gates < 2 ABUT == 0 REGION
}
DRC7_1 { @ Metal1 width = 3L
         INT metal1 < 3
}
DRC7_2 { @ Metal1 spacing = 3L
         EXT metal1 < 3
}
DRC7_3 { @ Metal1 overlap of contact to poly = 1L
         ENC cont2poly metal1 < 1 ABUT == 0 REGION
}
DRC7_4 { @ Metal1 overlap of contact to active = 1L
         ENC cont2active metal1 < 1 ABUT == 0 REGION
}
DRC8_1 { @ Via size exactly 2L X 2L
         NOT RECTANGLE via == 2 BY == 2
}
DRC8_2 { @ Via spacing = 3L
         EXT via < 3 SINGULAR
}
DRC8_3 { @ Via overlap by metal1 = 1L
         ENC via metal1 < 1 ABUT == 0 REGION
}
DRC8_4 { @ Via space to poly or active edge = 2L
         EXT via active < 2 ABUT == 0 OVERLAP
         ENC via active < 2 ABUT == 0
         EXT via poly < 2 ABUT == 0 OVERLAP
         ENC via poly < 2 ABUT == 0
}
DRC8_5 { @ Via spacing to contact = 2L
         EXT via cont2poly < 2 ABUT == 0 SINGULAR REGION
         EXT via cont2active < 2 ABUT == 0 SINGULAR REGION
}
DRC9_1 { @ Metal2 width = 3L
         INT metal2 < 3
}
DRC9_2 { @ Metal2 spacing = 4L
         EXT metal2 < 4
}
DRC9_3 { @ Metal2 overlap of via = 1L
         ENC via metal2 < 1 ABUT == 0 REGION
}