

Article 2409 of comp.lsi.cad:
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>From: [email-masked] (Gilles-Eric DESCAMPS)
Newsgroups: comp.lsi.cad,comp.lsi,comp.lang.vhdl,ibp.annonce,comp.lsi.testing,ibp.masi,eunet.esprit.eurochip,fnet.general
Subject: ALLIANCE 1.1
Message-ID: <[email-masked]>
Date: 16 Feb 93 13:17:34 GMT
Sender: [email-masked] (Le Facteur)
Organization: Laboratoire MASI, Paris VI, France.
Lines: 116
Xref: Intrepid comp.lsi.cad:2409 comp.lsi:1995 comp.lang.vhdl:931 comp.lsi.testing:332
Nntp-Posting-Host: cao-vlsi.ibp.fr

********************************************
* Announcement of a complete CAD System    * 
* for teaching VLSI Digital CMOS Design    *
********************************************

        Hi, VLSI folks

        ALLIANCE 1.1 is a complete set of CAD tools for teaching Digital 
CMOS VLSI Design in Universities. It includes VHDL compiler and simulator,
logic synthesis tools, automatic place and route, etc...  ALLIANCE is the
result of a ten years effort at University Pierre et Marie
Curie (PARIS VI, France).

	The complete ALLIANCE CAD Framework is available by anonymous FTP
at:

   ftp-masi.ibp.fr          in the /pub/cao-vlsi/alliance directory.
   ftp.ibp.fr               in the /ibp/softs/masi/alliance directory.

	ALLIANCE is pretty big, so before you download it, you'd
better get OVERVIEW.ps to examine its basic functionalities. OVERVIEW.ps
is a PostScript file that gives you a good idea of what ALLIANCE can do.
You should also get ALLIANCE.SETUP.ps, the PostScript file describing 
the installation procedure. Read it carefully.

	ALLIANCE is totally free, and includes C source files and online 
documentation (UNIX man).

	For the moment, Release 1.1 runs on SUN SparcStations (SunOS 4.1.1)
and requires about 50 Mbytes of disk space. For internal use, we have ported
ALLIANCE on DECsystem (Ultrix 4.3) and 386 PC (ISC3.2.2). 

	Our ambition with ALLIANCE is twofold:

	- allow Universities to teach the basics of VLSI design without
bothering about expensive commercial CAD tools. Chips as complex as the 32 bits
DLX microprocessor (Patterson & Hennessy) have been successfully implemented
using ALLIANCE tools.
	- provide to all people interested in designing innovative CAD tools
an open framework with all C sources available. A set of parsers/drivers
allows the users to convert common external standard formats (VHDL, SPICE,
EDIF, CIF, GDSII) to the internal, object-oriented, data-base used to
represent the three VLSI views: physical (layout), structural (netlist),
and behavioral.

        ALLIANCE allows VLSI designers to:
                - capture and simulate VHDL behavioral views.
                - capture and validate structural views.
                - produce physical layout.
                - verify layout (DRC).
                - check layout against structural (logical/extracted)
                and behavioral (formal proof) views.

        Each ALLIANCE tool can operate: 
                - as a standalone program
                - as a part of the complete Framework

        Available tools in the release 1.1 are:
                - asimut, a VHDL behavioral and structural simulator.
                - genpat, a simulation patterns procedural generator.
                - sclib, a complete symbolic standard-cells library.
                - genlib, a procedural language for netlist or layout capture.
                - scr, a place and route tool for standard-cells.
                - ring, a core-to-pads router.
                - s2r, a symbolic to real (micron) converter. Target
                  formats are GDSII and CIF.
                - versatil, a fast Design Rule Checker.
                - lynx, a layout extractor.
                - lvx, a logical/extracted netcompare tool.
                - desb, a functional abstractor/disassembler. Provides
                  a VHDL data-flow description from a transistor netlist.
                - proof, performs a formal comparison between two
                  behavioral VHDL descriptions.
                - alc, a hierarchical symbolic layout editor.
                - mbk2ps, produces PostScript files from layout.
                - logic, a complete logic synthesis tool. Provides a netlist
                  of gates from a VHDL behavioral description.

        Supported formats are:
                - Behavioral view VHDL parser and driver
                - Structural view EDIF, COMPASS, SPICE, and VHDL
                - Physical view COMPASS. GDSII and CIF are produced.

	A mailing-list is available to the users of ALLIANCE.
	To Subscribe or to unsubscribe to it please mail to 
	[email-masked] 
	To mail a message please mail to [email-masked]

        You may get ALLIANCE by two distinct means:
                1) by anonymous FTP
                2) by sending a blank tape with your complete affiliation 
		to the following address:

                   Laboratoire MASI/CAO-VLSI
                   Tour 55-65, 2eme etage, Porte 13
                   Universite Pierre et Marie Curie (PARIS VI)
                   4, place Jussieu 75252 PARIS Cedex 05
                   FRANCE

                                        MASI/CAO-VLSI CAD Team

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| Address  :                                                               |
|   Laboratoire MASI/CAO-VLSI                                              |
|   Tour 55-65, 2eme etage, Porte 13                                       |
|   Universite Pierre et Marie Curie (PARIS VI)                            |
|   4, place Jussieu 75252 PARIS Cedex 05                                  |
|   FRANCE                                                                 |
| Fax      : 33 1 44 27 62 86                                              |
| E-mail   : [email-masked]                                          |
| ftp site : ftp-masi.ibp.fr                                               |
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