Article 25371 of comp.arch:
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From: mmm@cup.portal.com (Mark Robert Thorson)
Newsgroups: comp.arch,sci.electronics
Subject: Re: Dynamic RAMs, static RAMs, FIFO queues
Message-ID: <58507@cup.portal.com>
Date: 5 May 92 07:02:40 GMT
References: <1992Apr22.145335.13100@irisa.fr>
Organization: The Portal System (TM)
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Xref: Intrepid comp.arch:25371 sci.electronics:29632

Modern FIFO's are not true FIFO's.  They're SRAM's with control logic
to run a ring buffer which emulates a FIFO.  The two big advantages
are denser layout (in larger FIFO sizes) and constant fall-through
delay.  WRT the former, an SRAM-based design has a certain fixed cost
for the control logic but a smaller incremental cost.  WRT the latter,
the old-fashioned "true" FIFO's often had ridiculously long fall-through
times as the data ripples through every stage of the FIFO.  Because you are
considering using DRAM, you must be talking about a deep FIFO, therefore
the cost of a FIFO is equal to an equal amount of SRAM plus a small constant.

As far as DRAM vs. SRAM goes, the cell is a transistor and a capacitor vs.
four or six transistors (depending on the design).  You can't compare them
quantitatively in the abstract because both are highly implementation dependent.
For example, a DRAM chip is made using a process highly optimized for
the memory chip design.  For example, it may have a step which cuts
deep trenches into the silicon, in order to make a structure with a
large surface area for use as a DRAM cell capacitor which doesn't consume
much of the area in the plane of the surface of the chip.