Article: 4653 of comp.lsi.cad
Relay-Version: ANU News - V6.1B10 07/27/94 OpenVMS AXP V1.5; site kuhub.cc.ukans.edu
Path: kuhub.cc.ukans.edu!caen!newsxfer.itd.umich.edu!gatech!howland.reston.ans.net!EU.net!sun4nl!news.nic.surfnet.nl!tudelft.nl!et.tudelft.nl!rschramp
Newsgroups: comp.lsi.cad
Subject: Re: anyone using OCEAN?
Message-ID: <1994Aug30.111120.4194@tudedv.et.tudelft.nl>
From: rschramp@et.tudelft.nl
Date: 30 Aug 94 11:11:20 +0200
References: <1994Aug29.121046.27619@usage.csd.unsw.OZ.AU>
Organization: TU-Delft, dpt of Electrical Engineering
Lines: 66

In article <1994Aug29.121046.27619@usage.csd.unsw.OZ.AU>, trevore@vast.unsw.edu.au (Trevor Elbourne) writes:
> I'd appreciate anyone who has used the OCEAN set of tools
> to design and fabricate a chip to relate their experiences.

I am a Student at the technical university of Delft and used the
OCEAN set of tools for designing a signed bit to 2's complement converter.
Most of the design was done in VHDL. 

> What I am really interested in is:
> 
> 	* the process used
> 	  (eg 0.8 um, triple layer metal etc .. )

I think it was 1um (It was the standard supplied fishbone which is
manufactured by Philips), I could use 2 metal layers and 2 contact layers
Metal1
Metal2
Connect1  Connects Metal1 to fishbone
Connect2  Connects Metal2 to Metal1
It's not allowed to put two Connect holes on top of eachother
> 
> 	* the gate array image used
> 	  (was it custom or one of the supplied eg fishbone)
> 
> 	* number of gates/transistors
I don't know how much were availeble (30.000 */ 10 I think). How much I used?
Not very much, I think about 2000 transistors (it is hard to keep track
because I used VHDL)

> 
> 	* any hassles with place & route
The automatic placer works but it isn't  extremely good: It doesn't
use any functional information from VHDL so it packs let say a
16 bit full adder in a square of 4 times 4  full adders, Zig Zagging
from left to right. So you have to give the placer some help. The
router is very good; At least I haven't had any problems with it. 
> 
> 	* any other helpful information/hints
Well err, what I did is that I created some cell in ocean, after
that I extracted it with some extraction tool, and used it in VHDL.
Sort of reverse engineering. I don't know if that's special?

> 
> The reason I ask is that I am evaluating the feasibility of using
> OCEAN for the 70,000 gate ASIC I am working on. The major hurdles
> seem to be choosing a target technology and getting OCEAN to use
> that technology, and creating an OCEAN library compatible with the
> library used during our schematic capture. Up until now we have been
> using Mentors Design Architect for schematic capture with VTIs VGC450
> gate array library. But we'd like to do the place and route ourselves
> (more control), so OCEAN seems a great choice.
> 
> Any advice/help would be greatly appreciated. Will post a summary
> of any responses I receive.

For more information there is a WWW server(mosaic) at the 17th floor
at TUDelft which contain's information on ocean.

> 
> Thanks in advance,
> Trevor Elbourne.
> 

Greetings Ruud Schramp
Student at Technical University of Delft