Article 21341 of comp.arch:
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From: mark@microunity.com (Mark Johnson)
Newsgroups: comp.arch
Subject: grand simplifications (interconnect)
Message-ID: <MARK.91Nov13095903@thalia.microunity.com>
Date: 13 Nov 91 14:59:03 GMT
References: <332@idtg.UUCP>
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In article <332@idtg.UUCP> dow@idtg.UUCP (Keith Dow) writes:
     > The problems of high speed design have not received the
     > attention they should from digital designers.  Nor are
     > they as simple as some people think.

Then he goes on to state as facts, a couple of simple empirical formulae:
     > The people who write CAD software also don't understand
     > interconnects.  The delay for the simple series circuit
     > of a battery, a switch, a resistor and a capacitor is 0.7RC.
     > If you interested in a long interconnect, the delay
     > due to it is about 0.4RC. (R is wire resistance, C is wire
     > capacitance).

What's missing of course is an explanation of where these
"Keith Dow Factual Numbers" came from.  The answers are:

  (A) For an R and a C and a battery and an ideal switch, the
      delay from the instant when the switch closes till the
      instant the capacitor voltage gets to the halfway point,
      is k*R*C where k=-ln(0.5), i.e. k=0.6931.

      Now if you happen to want to know (the delay to the halfway
      voltage), then 0.7RC is a reasonable approximation.

      Note that contemporary CMOS (i486 vintage) generally uses
      a "P to N ratio" which gives logic thresholds of about 0.45X
      of the supply voltage.  In its final incarnations, scaled
      NMOS (i286 vintage) gave logic thresholds of about 0.35X of
      the supply voltage.

      So for CMOS, use k*R*C with k=-ln(0.55)=0.6 for rising
      transitions and k=-ln(0.45)=0.8 for falling transitions.

      For NMOS, use k*R*C with k=-ln(0.65)=0.43 for rising
      transitions and k=-ln(0.35)=1.05 for falling transitions.

      Interestingly, none of the "k values" above, for actual IC
      logic families, is equal to Mr. Dow's magic constant 0.7.




  (B) For a distributed RC line (e.g. a long interconnect on an
      IC chip), which is characterized by a capacitance-per-unit-length
      C0 and a resistance-per-unit-length R0, then the delay from
      the instant when the switch closes till the instant the end of
      the wire gets to the halfway voltage, can be approximated by
      0.5 * Z * (R0 * L) * (C0 * L), where L is the length of the line
      and where Z=-ln(0.5), i.e. Z=0.6931.  Since the terms
      in parentheses are just the total resistance of the line R and
      the total capacitance of the line C, this reduces to 0.3466*R*C
      for (the delay to the halfway point).  Mr. Dow approximates it
      as 0.4RC.

      If the end of the line is to be sensed by a contemporary CMOS
      circuit with a logic threshold of 0.45X of the supply voltage,
      then for a rising transition the delay is approx 0.30RC and
      the delay for a falling transition is approx 0.40RC.

      If the end of the line is to be sensed by an NMOS circuit with
      a logic threshold of 0.35X of the supply voltage, then for a
      rising transition the delay is approx 0.215RC and the delay
      for a falling transition is approx 0.525RC.
--
     Mark Johnson       mark@microunity.com       (408) 734-8100