Subject: Part 1:Topic: ANNOUNCEMENTS

From: The MOSIS System <[email-masked]> (send requests to [email-masked])
Date: 12 April 1991 9:07:37

Your-message-sent: Fri, 12 Apr 91 11:00:29 CDT
Your-Message-ID: <[email-masked]>
MOSIS-Message-ID: imlr-00066361-91041209014800
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-- Message from file: MOSIS_DATA:[UMOSIS.CC.ANNOUNCEMENTS]MOSANN.TXT.3 --
   Thursday, March 14, 1991 03:19:50-GMT

N F  157 13-Mar [email-masked] NEW MOSIS DOCUMENTS (2205 chars)
 UF  156 13-Mar MOSIS AGENT     Files for older announcements (523 chars)
 UF  155 11-Mar [email-masked] GALLIUM ARSENIDE PROCESS UPDATE (6407 chars)
 UF  153 17-Jan [email-masked] 1991 STUDENT VLSI INTEGRATED CIRC (10950 chars)

Message 157 -- ************************
13-Mar-91 11:53:33-PST,2205;000000000000
Return-path: <[email-masked]>
Date: 13-MAR-1991 11:48:12
From: [email-masked]
Subject: NEW MOSIS DOCUMENTS
Bcc: [email-masked]
Reply-to: [email-masked]

Wednesday, March 13, 1991

 Files created in the past 30 days:

 108PIN-LAYOUT.INF        3414 11-Feb-91 17:45:05
 132PIN-LAYOUT.INF        3664 11-Feb-91 17:46:03
 ANNOUNCEMENTS-1988.INF
                         59917 13-Mar-91  9:50:30
 ANNOUNCEMENTS-1989.INF
                        104065 13-Mar-91  9:50:27
 ANNOUNCEMENTS-1990.INF
                         78501 13-Mar-91  9:50:25
 ANNOUNCEMENTS.INF       20568 13-Mar-91 10:58:38
 CHAPT10_TEMP.MSS         4270 11-Mar-91  8:34:39
 CMOSN.TECH              56642 27-Feb-91 17:30:04
 FOUNDRIES.INF             838 11-Feb-91 12:13:48
 LIBINF.DOC               9626 11-Mar-91 19:23:23
 N0BS.PRM                 6612 11-Feb-91 16:59:07
 N0BS.STS                  828 14-Feb-91  8:56:53
 N0CT.PRM                 7852 19-Feb-91  7:34:26
 N0CT.STS                  852 22-Feb-91  8:52:44
 N0CU.PRM                 6604 21-Feb-91  8:56:51
 N0CU.STS                  826 28-Feb-91  8:51:38
 N11A.PRM                 7866  6-Mar-91 11:32:58
 N11A.STS                  854 13-Mar-91  8:28:22
 N11B.PRM                 7862  7-Mar-91 10:09:17
 N11B.STS                  860 12-Mar-91  8:26:17
 N11C.STS                  882 11-Mar-91  8:57:08
 N11D.PRM                 7848  5-Mar-91 15:43:13
 N11D.STS                  852 11-Mar-91  8:56:30
 N11W.PRM                 7842 19-Feb-91 13:05:58
 N11W.STS                  852 25-Feb-91  8:36:28
 N11Y.PRM                 5516  4-Mar-91 10:11:31
 N11Y.STS                  826  8-Mar-91  8:45:11
 N11Z.STS                  842  8-Mar-91  8:35:48
 N12E.STS                  884 19-Feb-91  9:08:34
 N12F.STS                  852 27-Feb-91  8:38:57
 N12G.STS                  882  6-Mar-91  8:38:53
 PRICE_SCHED.INF         11902 14-Feb-91 10:44:50
 SCMOS.TECH             120316 20-Feb-91 16:39:42
 TINYCHIP.INF             4798 19-Feb-91  9:14:20
 VITESSE_GAAS.INF         2098 19-Feb-91  8:27:49
 VITESSE_GAAS_LIBRARY.INF
                          2230 11-Mar-91 10:36:44

[]

Message 156 -- ************************
13-Mar-91 10:06:28-PST,523;000000000001
Return-path: <[email-masked]>
Date: Wed 13 Mar 91 10:06:13-PDT
From: MOSIS AGENT <[email-masked]>
Subject: Files for older announcements
To: mosann.umosis@cheeta
Message-ID: <[email-masked]>
Mail-System-Version: <VAX-MM(227)+TOPSLIB(132)@Cheeta.ISI.Edu>

Announcements made before 1-Jan-1991 can be found in information files
named for the year they were made, as follows:

   ANNOUNCEMENTS-1990
   ANNOUNCEMENTS-1989
   ANNOUNCEMENTS-1988
   ANNOUNCEMENTS-PRE-1988
-------

Message 155 -- ************************
11-Mar-91 16:50:36-PST,6407;000000000004
Return-path: <[email-masked]>
Date: 11-MAR-1991 16:40:55
From: [email-masked]
Subject: GALLIUM ARSENIDE PROCESS UPDATE
Bcc: [email-masked]
Reply-to: [email-masked]

Dear MOSIS Users:

I. VITESSE GALLIUM ARSENIDE PROCESS

This is to announce online files describing the Vitesse Gallium Arsenide
process. These files are now listed in the TOPICS file:

		VITESSE_GAAS		Includes a description of the Vitesse
					E/D process, pointers to obtaining
					Magic technology files and a reminder
					that you need to make reservations
					for these runs.

		VITESSE_GAAS_HSPICE	HSPICE model parameters provided by
					Vitesse for their GaAs process.  
					(Only HSPICE models are made available
					by Vitesse.)

		VITESSE_GAAS_LIBRARY	Information on how to obtain the
					VCB50K standard cell library design
					kit through MOSIS.

To get these online files, send a message in the following format to
[email-masked]:

		REQUEST: INFORMATION
		TOPIC: TOPICS, VITESSE_GAAS, VITESSE_GAAS_HSPICE
		TOPIC: VITESSE_LIBRARY
		REQUEST: END

To obtain hardcopies of the Vitesse Design Rules, send an ATTENTION message
to [email-masked] and include your U.S. mailing address.

II. UCSB GALLIUM ARSENIDE LIBRARY and DESIGN COURSE

MOSIS would like to announce that the creation of a new library with pad
and example cells (e.g. NOR) from UCSB. This unsupported library is
for use with the UCSB Vitesse GaAs Magic technology file, which is available
under the topic EDGAAS.TECH

To get further information on this library, send a message in the following
format to [email-masked]:

		REQUEST: LIBRARY
		LIBRARY: UCSB_HGAAS2_PADS

		REQUEST: INFORMATION
		TOPIC:   EDGAAS.TECH
		REQUEST: END

In order to see if the highly successful GaAs IC design teacher's
course can be held again this summer, please reply to this message
indicating if you are interested or not. You should contact Steve Long
([email-masked]) if you need further information regarding the
course description or contents.

The course was first held at the University of California, Santa
Barbara during the summer of 1989. It provided an intensive
introduction to the design of GaAs digital ICs using the MOSIS foundry
services. Those who presently teach or are planning to teach GaAs IC
courses are the intended audience, however, GaAs IC users are also
welcome. No prior experience with GaAs devices or circuits is
required, however NMOS or CMOS IC design experience will be needed due
to the fast pace of the course.  The attendance will be limited to a
maximum enrollment of 40 with priority given to instructors.

The course will emphasize full custom design of GaAs digital ICs.  The MAGIC
layout editor, SPICE, and associated verification tools will be utilized for
the design projects.  The course will cover the following topics:

1.  Introduction to GaAs devices and models.
2.  Logic design principles and examples
3.  Interconnection design rules
4.  Test procedures for GaAs digital ICs
5.  Layout and simulation tools
6.  Layout design rules and the MOSIS interface
7.  A design project will be included.  

The projects will be submitted for fabrication to MOSIS and made available
for testing in packaged form in the fall. The class will use the McGraw-Hill
textbook, GaAs Digital IC Design, by S. Long and S. Butner.

III. MOSIS SERVICE FABRICATION SCHEDULE UPDATE

Also, please note the enclosed MOSIS service fabrication schedule which
has been extended through October, 1991.  

*******************************************************************************
			
		    THE MOSIS SERVICE FABRICATION SCHEDULE
			  (JANUARY - OCTOBER 1991)

JAN 2	1.2U HP				JUN 5	1.2U HP
JAN 9	2.0U ORBIT			JUN 12	2.0U VLSI TECH
JAN 9	2.0U ORBIT ANALOG		JUN 19	
JAN 16	VITESSE GAAS			JUN 26	2.0U ORBIT
JAN 23	2.0U VLSI TECH			JUN 26	2.0U ORBIT ANALOG
JAN 30
					JUL 3	1.2U HP
FEB 6	2.0U ORBIT			JUL 10	2.0U VLSI TECH
FEB 13	1.2U HP				JUL 17	VITESSE GAAS
FEB 20	2.0U VLSI TECH			JUL 24	2.0U ORBIT
FEB 27					JUL 31

MAR 6	2.0U ORBIT			AUG 7	2.0U VLSI TECH
MAR 6	2.0U ORBIT ANALOG		AUG 14	1.2U HP
MAR 13	1.2U HP				AUG 21 	2.0U ORBIT
MAR 20	2.0U VLSI TECH			AUG 21	2.0U ORBIT ANALOG
MAR 27					AUG 28

APR 3	2.0U ORBIT			SEP 4	2.0U VLSI TECH
APR 10	1.2U HP				SEP 11	1.2U HP
APR 17	2.0U VLSI TECH			SEP 18	2.0U ORBIT
APR 24	VITESSE GAAS			SEP 25

MAY 1	2.0U ORBIT			OCT 2	2.0U VLSI TECH
MAY 1	2.0U ORBIT ANALOG		OCT 9	1.2U HP
MAY 8	1.2U HP				OCT 16	2.0U ORBIT ANALOG
MAY 15	2.0U VLSI TECH			OCT 16	2.0U ORBIT
MAY 22					OCT 23	VITESSE GAAS
MAY 29	2.0U ORBIT			OCT 30	2.0U VLSI TECH

-------------------------------------------------------------------------------
	
1.6 MICRON RUNS are not included in this schedule because they are initiated
when enough projects have been received to fill them.  When MOSIS schedules
the run, you will be asked to confirm your project size.   Cancellations
cannot be accepted after the run has been scheduled.  Your MOSIS account will 
be charged at this time.

TO ENSURE SPACE ON 1.2, 1.6 MICRON AND GAAS RUNS, call or send  an ATTENTION
message to Sam Reynolds and include the estimated project submission date and
the width and height of your project in millimeters. Because space is limited
on these reticle runs,  priority will be given to those projects with 
reservations.

2.0 MICRON DOUBLE POLY RUNS support both double and single poly designs.

SCHEDULE CHANGES / PROJECT SUBMISSIONS:  MOSIS will make every attempt to keep
this schedule, however, changes may be unavoidable.  For schedule confirmation
contact Sam Reynolds at (213) 822-1511.  See the MOSIS Technology Sheet for
more information on project submissions.

KEY TO PROCESS NAMES:
	Process Name:	     Technology:             Fabricator:
	2.0U VLSI            CMOS N-WELL      	   VLSI TECHNOLOGY
        2.0U ORBIT           CMOS P-WELL, 2 POLY   ORBIT
        2.0U ORBIT ANALOG    CMOS N-WELL, 2 POLY*  ORBIT
	1.2U HP		     CMOS N-WELL           HEWLETT-PACKARD
	1.6U HP		     CMOS N-WELL           HEWLETT-PACKARD
	VITESSE GAAS	     GALLIUM ARSENIDE      VITESSE

PRODUCTION ORDERS: Contact Kathleen Fry at (213) 822-1511 to receive a quote
for an entire wafer lot.

*(Low Noise Analog)

The MOSIS Service
February, 1991
-------

Message 153 -- ************************
17-Jan-91 11:25:04-PST,10950;000000000004
Return-path: <[email-masked]>
Date: 17-JAN-1991 11:18:31
From: [email-masked]
Subject: 1991 STUDENT VLSI INTEGRATED CIRCUIT DESIGN CONTEST
Bcc: [email-masked]
Reply-to: [email-masked]

1991 STUDENT VLSI INTEGRATED CIRCUIT DESIGN CONTEST
GENERAL INFORMATION

1.  The purpose of this contest is to promote excellence in education
for integrated circuit designers at universities throughout the
United States and foreign countries It is specifically intended to
provide competition between students who are participating in classes
and in research that design and fabricate integrated circuits.
Students that use the MOSIS foundry with joint educational funding
from NSF and DARPA for the actual fabrication of integrated circuits
are specifically encouraged to enter the contest. However, circuits
that have been fabricated from other sources are also acceptable. In
addition, circuits that have been designed and tested using Field
Programmable Logic Arrays are also acceptable.

2.  The contest will be split into two groups, a "novice class" and an
"experienced class". The novice class is intended for students who
are taking an introductory first quarter/semester class in which they
design an integrated circuit.  The experienced class is intended for
students that have already completed the introductory class and
are continuing in an advanced class or students that are actually
doing research that involves the design and fabrication of integrated
circuits.

3.  We will accept two entries in both the novice and the experienced
classes from each University (a total of four from any university).
These entries can be from the same or different departments.  Entries
are due at the office of Dr. Kent F. Smith at the University of Utah
by June 15, 1991.

4.  The contest will be held in conjunction with the Microelectronic
System Education Conference at San Jose in late July, 1991 (the actual
date is yet to be determined).  Each student must submit a written
report (details are shown below) and a poster for display at the
conference.  We suggest that each university or possibly a group of
interested universities meet together and hold a preliminary contest
before May 15 for purposes of selecting their entries.  The individual
universities or groups of universities may want to arrange for
donations of cash and/or equipment from companies in their locality
for their local contest.

5. Interested universities should use the same set of rules for
judging which are attached to provide consistent criteria for eventual
submission to the national contest. It is a requirement that the
circuits be fabricated and tested prior to submission to the contest.
The reports should detail the results of the testing.

6.  The conference is not providing any funds for travel expenses.
Each department at the students respective University should provide
enough cash through donations or department budgets to cover the
expenses for their students to come to Santa Clara.  No cash prizes
will be awarded at the Conference but the entries will be judged at
the conference and participants will receive national recognition.

7.  There will be a 1st, 2nd, 3rd and 4th place winner picked from
each of the novice and the experienced groups.  We will ask the 1st
place winners in each of the two groups to present their papers to the
conference.  This means that the 1st place winners must be in
attendance at the conference.  Other winners need not be in attendance
but we do encourage attendance of the students.

6.  All posters will be displayed at the conference and all students
that are attending will be given an opportunity to stand by their
posters to explain their work to both the judges and to other
interested parties.


CRITERIA FOR ENTERING THE CONTEST

1.  The contest is for any full time graduate or undergraduate student
at any university in the United States.  Students are eligible to
enter, provided they had not, before the completion of their projects,
been employed as integrated circuit designers in industry or in
full-time VLSI design positions at their respective universities.

2.  To be eligible for the contest, a chip must meet functional needs
and be non-proprietary. The chips must be fabricated and tested.  The
results of the testing must be reported even if they were negative.

3.  All work on the project must be done using facilities, equipment
and design tools provided or supplied by the respective university.
Any design style supported at the university may be used, including,
full-custom, standard-cell, symbolic and compiled, FPGAs, etc.

4.  Judging will be based upon a written report and a poster.  The
written report must conform to the specified outline (see
attachment), and must total no more than 8 pages for the novice class
and 12 pages for the experienced class. The reports must be sent to
Dr. Kent F. Smith at the University of Utah by June 15, 1991.
Material for the poster must be placed on a 32 inch X 32 inch poster
board.  Poster boards will be available at the conference so it
is suggested that you bring your material and assemble the poster at
the conference.  The poster must be in place after the first day of
the conference to give the judges sufficient time to review them.



REPORT SPECIFICATIONS AND HINTS

Each report shall be a total of no more 8 pages for the novice class
and 12 pages for the experienced class including title page, text,
figures, etc.; no pages beyond this will be accepted. Text should be
10 pt and double spaced.  The pages must all be 8.5 X 11 inches,
except one optional(for a layout) which may fold out as large as a C
size sheet.  Each paper is expected to follow the form specified
below, including all items appropriate for the specific project.

Since projects are judged solely upon the written reports, clarity and
completeness of the report are of paramount importance.  Spelling and
grammatical errors will not be impressive.  Writing style should be
clear and concise.  Remember that the judges' expertise may not be in
the area of your project.  Make your explanations straightforward and
understandable.

Design for testability is an important issue.  Discuss approaches you
took for testing and testing issues you have considered in the
design. Engineering specifications and performance statistics can be
efficiently presented in tabular form.  For chip designs, the
following should be considered:

1.  Environment (temperature and voltage ranges)

2.  Project Statistics (total power, number of transistors, die size)

3, Timing and Critical Paths --- What clocking scheme is used?  Why?
What is the clock frequency?  Which paths are critical?  Have you
simulated or measured their timing?  Even if you do not have tools to
do so, at least explain where potential problems might be.



REPORT OUTLINE

1.  Title Page (a page by itself)

2.  Abstract (no more than a 1/2 page, on a page by itself)

3.  System Overview: Chip in its Environment.  Include motivation for
the chip.  Is VLSI appropriate?  Does this design satisfy the system
requirements?  What novel ideas or elegant solutions does the design
include?

4.  Implementation (bulk of the report)

       	Engineering considerations (specifications, tradeoff, I/O
       	considerations, etc. --- see hints below)

       	Block Diagram, Logic / Circuit Diagrams, and Algorithms
       	Final Layout Plot (Not required but detail density of custom
       	layout, floor-planning / interconnect approach, point out
	features which need more explanation)

       	Verification and Simulation (keep it brief --- use explanation
       	with data)

       	Testing (How did you test this part with I/O pins only?
       	What test equipment did you use?)

       	Actual test results should be summarized.

       	Emphasize engineering tradeoffs. (What is unique about this
       	project?  Emphasis should be placed on why you did what you
	did.)
       
       	You may want to include statistics about your chip, i.e.  chip
	size, number of transistors, maximum clock speed, etc.

5.  Summary

6.  References


JUDGING CRITERIA

Entries will be judged on the following criteria, with weights as
shown:

1.  50% - Soundness of engineering, including evaluation of trade-offs
and ingenuity at all levels of design activity.  (Note that ingenuity
is usually seen in simplicity, rather than added complexity.)

2.  30% - Clarity of the functional specification, system description,
and chip (CAD tool) description.

3.  20% - Producibility and testability of the chip including
explanations of any special test procedures you have included to make
the part producible.


ENTRY FORM

1991 NATIONAL STUDENT VLSI "Novice Class" DESIGN CONTEST

Project Name: _________________________________

Entrants Name: _________________________________

Signature: _________________________________

Contact Person: _________________________________