1. What is MOSIS? 1.1. Introduction The MOSIS Service is a prototyping service offering fast-turnaround standard cell and full-custom VLSI circuit development at very low cost. MOSIS has developed a methodology that allows the merging of many different projects from various organizations onto a single wafer. Therefore, instead of paying for the cost of maskmaking, fabrication, and packaging for a complete run (currently between $50,000 and $80,000) MOSIS users pay only for the fraction of the silicon that they use, which can cost as little as $400. MOSIS' ease of access, quick turnaround, and cost-effectiveness have afforded designers opportunities for frequent prototype iterations that otherwise might not even have been considered. 1.2. State-of-the-Art Technologies Wafer fabrication runs are scheduled on a regular basis for 3.0, 2.0, 1.6, and 1.2 micron double metal CMOS/Bulk technologies. A CMOS/Bulk double poly capacitor option for analog design is also available. The MOSIS vendor-base includes multiple fabricators for all technologies, and prototyping is alternated between them. Several sets of design rules are supported, allowing designs done to MOSIS' own public-domain scalable rules, a set of DoD-developed scalable rules, and a fabricator's own rules to be combined on the same wafer fabrication run. The scalable CMOS rules allow designers to move from mature 3.0 micron to more advanced 2.0, 1.6, and 1.2 micron technologies. Those who wish to design for a multivendor base using the MOSIS scalable rules have the benefit of not being tied to a particular vendor, which allows direct comparison of vendor turnaround, yield, and cost. After prototyping, they can choose among vendors for production. Other designers prefer to work with a particular vendor, e.g., in order to utilize that vendor's design tools. MOSIS offers the option of selecting which fabricator a design will go to. MOSIS distributes DoD-developed standard cell libraries (3.0, 2.0, and 1.2 microns). CAD vendor support is available for the 3.0 micron library (CMOS3 Cell Library) and is in development for the 2.0 and 1.2 micron library (CMOSN). 1.3. How MOSIS Works MOSIS users request information from MOSIS on authorization, technologies, and schedules, and submit layout geometry in digital format on magnetic tape or via electronic mail. Within weeks, MOSIS delivers to users a set of bonded and packaged integrated circuits, which contain the design exactly as submitted to MOSIS (see the illustration at the end of this chapter). MOSIS merges designs submitted from different organizations onto one multiproject wafer (see photographs at the end of this chapter). Projects from the same organization can also be grouped onto one chip, called a multiproject chip. MOSIS will fabricate a design on the next available run of the requested technology, according to a published fabrication schedule. MOSIS checks for correct syntax upon receipt of the layout geometry but does not validate designs. After aggregating projects for a particular run, MOSIS writes tapes and sends them to the maskmaker for E-beam phototooling. Masks are then delivered to MOSIS for inspection and subsequently forwarded to the appropriate fabrication line. 1.4. Quality Control Mask vendors are required to do an automated inspection and masks are bought against industry defect density specifications. MOSIS runs its own process monitor as well as a yield monitor on every run, buying wafers against parametric specifications that are checked by both the vendor and MOSIS. Information obtained from the yield monitor is maintained in statistical control charts to help select vendors and to continuously monitor vendor quality. Once probed and accepted, the selected wafers are sent to a packager for assembly. Chips are wire-bonded according to either a standard MOSIS bonding map or one designed by the user. MOSIS packagers are qualified on the basis of bond pull tests and must follow strict static electricity control procedures in handling users' projects. MOSIS requires that its packaging vendors meet industry visual inspection criteria. Packaged parts are sent to MOSIS users with process parametric data and SPICE simulation parameters from their particular wafer lot. 1.5. Background MOSIS is an acronym for MOS Implementation System. The MOSIS Service, begun in 1980, provides fabrication services to government contractors, agencies, and university classes under the sponsorship of the Defense Advanced Research Projects Agency (DARPA) with assistance from the National Science Foundation (NSF). The MOSIS user-base was initially primarily university and government users. However, MOSIS' success in serving this group of users led, in recent years, to a natural expansion into the industrial sector, with a rapidly growing use of MOSIS by commercial companies. MOSIS foundries have also taken advantage of the frequent prototype runs for their own needs as well as those of their clients. MOSIS is located at the Information Sciences Institute of the University of Southern California (USC/ISI) in Marina del Rey, California. 2. Becoming a MOSIS User AUTHORIZATION AND ACCOUNTING 2.1. Introduction This chapter describes how to become an authorized MOSIS user. Your authorization comes either from your company, in the form of a purchase order to MOSIS, or from the Defense Advanced Research Projects Agency (DARPA) or the National Science Foundation (NSF). 2.2. How to Become a MOSIS User Information on MOSIS can be acquired without being an authorized MOSIS user. If you have computer network access, simply send a message to MOSIS@MOSIS.EDU (on the Internet) and MOSIS will reply with a message indicating the format for MOSIS information requests. Other users may refer to the list of topics in the Reference Section (see page 87) and may request hardcopies of documents from the contacts listed at the end of this chapter. If you have any additional questions, please contact our User Liaison. 2.2.1. Commercial Accounts To contract directly with MOSIS for fabrication services, fill out two copies of the MOSIS Customer Agreement Form. Both copies of the agreement should be signed by your authorized representative and returned to us. MOSIS will sign both copies and return one to you. Once the signed Customer Agreement Forms have been received by MOSIS, you may submit your projects with a purchase order. A sample of the Customer Agreement Form is in Chapter 13, Section 13.2. You must request two Customer Agreement Forms from the MOSIS User Liaison (do NOT use copies of the sample one in the Reference Section). 2.2.2. Government-Sponsored Use of MOSIS Government-sponsored use of MOSIS may be available to the groups listed below. Applications for government-sponsored use are available from the MOSIS User Liaison and are entitled "Application to Use DARPA/NSF Service (MOSIS) for Fabrication of Prototype Quantities of Custom Integrated Circuits to Support Research" (or "to Support Education"). To obtain either of these two forms, see Section 2.4 at the end of this chapter. - DARPA and NSF Contractors: Organizations with DARPA or NSF contracts may apply for government-sponsored use of MOSIS with the MOSIS application form for Research. - Other Government Contractors: Government contractors not sponsored by DARPA or NSF may have their funding agency transfer funds to DARPA to cover the cost of their use of MOSIS. Contractors should estimate this cost on the Research form. The original of this form should be sent to MOSIS, and a copy should be sent to DARPA along with the transferred funds. - Government Agencies: Government agencies may transfer funds to DARPA to cover the cost of their use of MOSIS. Agencies should estimate the cost of their use of MOSIS using the Research form. The original of this form should be sent to MOSIS, and a copy should be sent to DARPA along with the transferred funds. - Universities Teaching VLSI Design Classes: Universities that are teaching classes in VLSI design may apply for government-sponsored use of MOSIS with the MOSIS application form for Education. 2.3. Getting Started - Your MOSIS Account You will be given a MOSIS account when (1) MOSIS receives two signed Customer Agreement Forms from you, or (2) DARPA or NSF asks MOSIS to set up an account. You will be supplied with an account number and other account parameters at that time. You will be authorized to spend a specific amount of money for MOSIS services. This amount will be based on (1) the amount of your purchase order, (2) the amount funded by NSF or DARPA, or (3) the amount transferred to DARPA by your sponsoring agency. 2.3.1. Additional Information and Documentation This manual is available online. Chapter 4 discusses online information retrieval in more detail. Many of the documents can also be requested in hardcopy for those who do not have online access. 2.3.2. Submitting Designs Designs from government-sponsored users must be submitted to MOSIS in CIF (Caltech Intermediate Form) via electronic mail. Users who are contracting directly with MOSIS may submit designs via electronic mail or on magnetic tape in GDSII, CIF, or MEBES format. 2.4. For More Information In this chapter we have given you an outline of the procedures necessary to get started with MOSIS. For additional information, send an Attention message to MOSIS (see Chapter 4) or contact any of the following MOSIS staff members with questions or documentation requests. General Information Sam Delatorre (User Liaison) Internet address: Delatorre@Mosis.Edu Tel: (213) 822-1511 Order Information Kathleen Fry (Operations Manager) Internet address: Fry@Mosis.Edu Tel: (213) 822-1511 Documentation Requests Christine Tomovich (Documentation Coordinator) Internet address: Tomovich@Mosis.Edu Tel: (213) 822-1511 3. Submitting Your Design to MOSIS DESIGN SUBMISSION - VIA MAGNETIC TAPE OR ELECTRONIC MAIL 3.1. Introduction This chapter describes how to submit your layout geometry for a MOSIS fabrication run. If you are not on an electronic network, you need to put your geometry on magnetic tape and mail it to MOSIS with a Project Submission Form containing important project information. (A sample of this form is in the back pocket of this manual.) To obtain an up-to-date form, contact the Documentation Coordinator (see page 10). If you are sending your files over an electronic mail network, you need to read Section 3.3, Network Users, which describes how to send files to MOSIS; this should be read in conjunction with Chapter 4, The MOSIS Mail System. Whether you are sending project design files to MOSIS on a magnetic tape or over the network, the list of MOSIS Command Language parameters in the Reference Section (see page 113) can be used as a checklist to make sure that you have taken care of all aspects of design submission. You should also review whether you have any special handling or bonding requests. It is important to consider these packaging requirements before project submittal. 3.2. Offline Users MOSIS accepts designs submitted on magnetic tape in GDSII, CIF (Caltech Intermediate Form), or MEBES format. Make sure your tape has a physical label on the outside. This label should include your name, affiliation, project name, and Project-ID, as well as technology (e.g., CBPM, SCP, SCN, SCE). Please review the technologies in Chapter 6. Fill out the Project Submission Form and have it signed by your authorized representative. Mail the labeled tape, Project Submission Form, and bonding diagram (if applicable) to: USC/Information Sciences Institute The MOSIS Service 4676 Admiralty Way Marina del Rey, CA 90292-6695 Attn: MOSIS Liaison 1. If you are using a MOSIS Standard Frame: MOSIS will generate a bonding diagram for you. You will need to indicate the Standard Frame name, e.g., 28PC23x34, on the Project Submission Form. (See Chapter 9 for a discussion of Standard and Nonstandard Frames.) 2. If you are using a Nonstandard Frame: You MUST submit a bonding diagram with your tape so that MOSIS knows exactly how you want your chip bonded. See sample bonding diagrams on page 69. Sample bonding diagram forms are in the back pocket of this manual. 3.3. Network Users MOSIS accepts designs from network users in CIF format. Project submission is accomplished through the MOSIS automatic message system, often in conjunction with FTP (File Transfer Protocol). All necessary files and information MUST be received and processed by MOSIS by 7:00 a.m. on the day of run closing. With this deadline in mind, it is important to consider your mode of file transfer and the particular characteristics of your network. MOSIS is on the Internet (previously called the ARPANET) and can be accessed by many other networks. The MOSIS automatic message software is called the MOSIS Command Language system. This software allows MOSIS to handle large amounts of user mail and to begin to process projects for fabrication. The next chapter in this manual describes in detail how to use this software to communicate with MOSIS. As a MOSIS user you need a mailbox on either the Internet or a system with a mail relay to the Internet. This chapter will discuss which network you are on and how to find a network path to MOSIS (see the illustration at the end of this chapter). 3.3.1. MOSIS and Computer Networks Some of the major networks that have access to the Internet through mail relays are listed below. - INTERNET: This network is sponsored by DARPA (the Defense Advanced Research Projects Agency) and NSF (the National Science Foundation) and has been in operation since 1969. Many government agencies, universities, and commercial companies are on this network, previously referred to as the ARPANET. Many individual networks are connected by gateways to form the Internet (e.g., MILNET, SATNET, WBNET, and many university networks). The network is managed by SRI Network Information Center. - BITNET: This network is sponsored by a consortium of universities and is managed by EDUCOM. - CSNET: This network is sponsored by a consortium of universities and contains university, industrial, and government research organizations. CSNET is managed by UCAR. - UUCP: This is a decentralized network system. It relies on phone calls and modems to communicate between sites. It is free and has mail relays to most of the other networks; however, mail transfer is often very slow, taking up to two or three days. 3.3.2. Finding the Network Path to MOSIS If you have mail relay access to the Internet, you must find out which network your computer is on and the mail path from it to MOSIS. Which network am I on? If your machine is not on a site on any of the above-mentioned networks, your machine may be a site on a local network. One of the sites on this local network may be already serving as a gateway to a remote network. To find out this information, contact your system administrator. Correct pathname MOSIS is on the Internet. If you have access to the Internet, UUCP, CSNET, or BITNET, you can send mail to MOSIS through one of the following paths: Network Network Address INTERNET mosis@mosis.edu BITNET mosis%mosis.edu@cunyvm.cuny.edu CSNET mosis%mosis.edu@relay.cs.net UUCP ...!{harvard,rutgers,seismo,sun,uiucdcs,talcott}mosis.edu!mosis (where"..." is your path to the computer listed after the "!".) 3.3.3. Network Contacts Network Network Contacts INTERNET Network mail: nic@sri-nic.arpa Tel: (800) 235-3155 BITNET Network mail: info%bitnic.bitnet@cunyvm.cuny.edu Tel: (609) 520-3377 (EDUCOM) CSNET Network mail: cic@sh.cs.net (CSNET Coordination and Information Center - CIC) Tel: (617) 497-2777 UUCP Network mail: Rick@uunet.uu.net Tel: (703) 276-7900 3.3.4. Sending the Message - Mail Size Limits and Internet Address Syntax At this time, no single item of mail having more than 900,000 characters can be sent to or from MOSIS. However, this limit does not apply to the transfer of CIF files via the CIF-FTP-Path specification. The Internet mail syntax has certain requirements that must be followed. Two of the main points are listed below: 1. The address parameter must fit on one line of less than 200 characters; address "folding" is not supported. 2. The special characters , , and may not be part of the address(es) even if part of a quoted string or quoted pair. For more details on syntax specifications, see the section at the end of this chapter entitled For More Information and note the article by David Crocker, "Standard for the Format of ARPA Internet Text Messages," which is available from the Network Information Center (NIC). If you are not directly connected to the Internet, the net-address given must be the name of the mailbox on the Internet host that acts as the mail relay between your network and the Internet. Although net-address syntax may vary in the message header, and according to your particular network path, the body of a request message (i.e., syntax) should be the same on every network. MOSIS has an automated information retrieval service for communicating with MOSIS users. This service allows you to request information on various topics, submit your project, and receive status reports on your design submission. This service uses a syntax called the MOSIS Command Language and is covered in detail in Chapter 4. The MOSIS Command Language software will read the address parameter specification and automatically use it as the reply path. 3.3.5. Reply Paths Check the following table to find the path you need to specify to enable MOSIS to reply to you. Please note that Internet addresses have a domain extension, e.g., .EDU, which indicates a domain or group of users with a similar affiliation (in this case, EDUCATION). Network Net-address INTERNET user@site.arpa (or other domain extension, e.g., .EDU) BITNET user%site.bitnet@cunyvm.cuny.edu CSNET user%site.csnet@relay.cs.net UUCP site3!site2!site1!user@{harvard,rutgers,seismo,sun,uiucdcs, talcott Rutgers(= RED.RUTGERS.EDU) and Seismo(= SEISMO.CSS.GOV) are the most popular UUCP relays. UUCP is the most complex of the nets and the user is more responsible for knowing his/her net paths to and from the Internet. Because networks are dynamic and also not foolproof, it is important to give yourself plenty of time when submitting geometry to a MOSIS run. Avoid sending very large files to MOSIS at the last minute. If there are network problems, you will need time to resend your design and still make the run schedule deadline. 3.4. For More Information DDN New User Guide, December 1985. NIC 50001, DDN Network Information Center, (800) 235-3155. Abrams, Marshall, and Ira W. Cotton, Computer Networks. IEEE Computer Society, 1987. (IEEE order no. 568.) Quarterman, John S., and Josiah C. Hoskins, "Notable Computer Networks" Communications of the ACM, vol. 29, no. 10, October 1986. Postel, Jon, Simple Mail Transfer Protocol. *RFC 821, SRI Network Information Center. Crocker, David H., Standard for the Format of ARPA Internet Text Messages *RFC 822, SRI Network Information Center. * Requests for RFCs should be addressed to NIC@SRI-NIC.ARPA or call 800-235-3155. 4. The MOSIS Mail System LEARNING THE MOSIS COMMAND LANGUAGE 4.1. Introduction Online users can request information, submit projects, ask for the status of a wafer run, or ask questions of the MOSIS staff, by sending electronic mail messages to MOSIS. Software developed by MOSIS, using a format called the MOSIS Command Language, interprets these requests automatically. This enables MOSIS to serve thousands of users with a very small staff. Although this chapter is primarily of interest to network users, offline users may be interested in noting the various fabrication steps and the kinds of information available from MOSIS. Of course, all users are welcome to contact the MOSIS Liaison or other appropriate MOSIS staff with special questions or requests. 4.2. Accessing MOSIS Prospective users can send an initial message to MOSIS and retrieve information on various topics without being an authorized user. Messages should be sent to the MOSIS address: MOSIS@MOSIS.EDU 4.2.1. First Message A first message to MOSIS usually contains regular text, that is, the message is not in MOSIS request format: ___________________________ | From: Dave@Navy | | To: mosis@MOSIS.EDU | | Hello, is anyone there? | ___________________________ MOSIS' Response MOSIS will respond with the following message, which includes samples of different information requests. _______________________________________________________________________________ | | | From: MOSIS@MOSIS.EDU | | Subject: WELCOME TO MOSIS! | To: Dave@Navy | | | Dear user: | | To request information, submit projects or find the status of a wafer | run, send an electronic mail message to MOSIS@@MOSIS.EDU in the following | 'REQUEST' message format: | | REQUEST: INFORMATION | TOPIC: TOPICS | REQUEST: END | | The MOSIS software automatically interprets these REQUEST messages and | replies with the specific information. For this reason, it is important | that your message syntax be accurate. Each message should end with a | 'REQUEST: END'. | | If the body of messages sent to your system is required to be below a | certain number of lines or characters, include the LINE-LIMIT and | BYTE-LIMIT parameters in your request messages and fill in the | appropriate value(s). MOSIS will fragment its response to your | request(s) into several individual messages to meet your system's | requirements, e.g., | | LINE-LIMIT: 50 | BYTE-LIMIT: 2000 | | If you have questions or special requests that require the attention | of the MOSIS staff, send an ATTENTION message in the following format: | | REQUEST: ATTENTION | (Put message here) | REQUEST: END | | Do NOT include any ':'s in the message portion of your ATTENTION | REQUEST or the MOSIS software will attempt to parse your message. The | MOSIS Liaison will then receive an incomplete message. | | The MOSIS Service | ------------------------------------------------------------------------------- 4.3. Request Message Format As show above, the format of a request is basically the same for all messages. Each message to MOSIS may contain several requests, each of which may in turn contain several parameters as arguments for the requests. See Section 13.3.2 of the Reference Section for sample messages to MOSIS. 4.3.1. Three Fields There are three parts to a request message: (1) the request field, (2) the parameter field(s), and (3) the end field. - A single message may contain different requests. A list of the available requests is given in Section 4.5 of this chapter. - Each request has various parameters that can go with it. For example, 'REQUEST: ATTENTION' may be followed by such parameters as 'ID' or 'P-PASSWORD'. See Section 13.3 of the Reference Section for request templates with their available parameters. - The "END" request marks the end of requests in a message. Please note that any text written after this line will be ignored. Therefore, do not append two or more requests together without removing the "REQUEST: END" line between them; otherwise, ONLY the first request will be seen by MOSIS. - All request and parameter names may be abbreviated, as long as there are no ambiguities. 4.3.2. Keep in Mind All MOSIS Request and Parameter names are case independent. No control codes other than , , , or should be used. No line should begin with "XXX:" unless "XXX" is a keyword as described above (i.e., "REQUEST" or a parameter). It is recommended that requests include the type of request and the Project-ID in the SUBJECT field of your message (use the project name if you have not yet been assigned an ID). This will facilitate searching through a series of messages if the MOSIS staff needs to find a particular message that you sent in. 4.3.3. Net-Address Parameter MOSIS sends replies to your messages to the NET-ADDRESS, a parameter specifed for your project in the NEW-PROJECT request. This is always true, unless there is a problem with the NET-ADDRESS parameter or the specified ID is not valid (does not exist or is not accompanied by the proper P-PASSWORD). In this case, MOSIS directs responses to the SENDER of the request. 4.4. Project Submission Sequence You should understand the MOSIS request system as it relates to the entire project submission sequence. Section 13.3 of the Reference Section gives more details on each request template; you should review this section before proceeding with project submission to MOSIS. There are four states within the submission sequence that define primarily whether MOSIS has a valid CIF file for your project and where this file is in the sequence. The following sections describe some of the major MOSIS requests in the context of these four states: 1) Before Valid CIF 2) Valid CIF (Accepted by MOSIS) 3) CIF Queued for Fabrication 4) Being Fabricated The New-Project Request The first request to MOSIS is usually the NEW-PROJECT request. MOSIS replies to this message by assigning you a Project-ID (e.g., 12345) in its reply. You MUST refer to this Project-ID in all subsequent communications to MOSIS concerning this project. 2. Valid CIF (Accepted by MOSIS) Checking your CIF File To check the validity (syntax) of your CIF file before fabrication, use the SUBMIT request. This submits your file for a syntax validation check called CHECK_PROJ. You may then use the FABRICATE request or, if there are problems with your file, you may correct and resubmit it. Updating CIF To update CIF, simply resubmit it (using the SUBMIT or FABRICATE request). If your CIF was submitted in fragments, however, you must use the DELETE-CIF command before resubmitting. Use this command request also when you have submitted a bad fragment and want to change it. This does NOT cancel your project. The Update Request To change one or more parameters to your project, e.g., SIZE, use the UPDATE request. This does NOT affect your CIF file. (TECHNOLOGY or LAMBDA parameters cannot be changed with this request.) 3. CIF Queued for Fabrication The Request for Fabrication After receiving your Project-ID, you may submit your CIF for syntax check and subsequent fabrication. If your CIF is valid, you will receive an acknowledgment from MOSIS that your project is queued for fabrication. (If your CIF fails the syntax check, you will also be notified.) Note that this message includes a new ID, called a Fab-ID which identifies the wafer lot of your project. A Fab-ID (for example, "M11XAA1") consists of three parts: a four-character Run-ID ("M11X"), a two-letter Chip-ID ("AA"), and a project number ("1") on the chip. If you are sharing a chip, your project could be 1 through 4. A run is also given a nickname (e.g., "Xerxes") for easy reference (and for fun!). This four letter Run-ID (referred to in this manual as "M11X") is assigned to each distinct mask set used to fabricate a lot (a set) of wafers. If you have requested that a chip be refabricated on another run, you will receive a new fabrication announcement with a new Fab-ID which retains the Chip-ID and assigns a new Run-ID. Cancelling Fabrication If you decide, after issuing the FABRICATE request, that you want to cancel fabrication, use the CANCEL-FABRICATE request. You MUST do this before you resubmit a new CIF for fabrication (under the same Project-ID). If you want to cancel your entire project, use the CANCEL-PROJECT request. 4. Being Fabricated Status Request Use the status (STS) request to ask for estimated fabrication and project delivery dates for your particular run (REQUEST: M11X.STS). Probe Request Vendors probe each wafer lot to ensure that wafers meet their specifications. MOSIS then does its own parametric probing using MOSIS test structures, making sure that wafers meet the fabricator's electrical parameter specifications and MOSIS' requirements. You can request probing results for a wafer lot (for example, lot M11X) by including REQUEST: M11X.PRM in an INFORMATION request. Delivery of Packaged Chips When device packaging is complete, MOSIS delivers your packaged chips to you, along with information describing the characteristics of your particular wafer lot. This information package includes a summary of the electrical characteristics of the wafer lot, a SPICE and/or BSIM deck, and a bonding diagram. Report Request After you have received your packaged parts and tested them, send MOSIS your test results in the form of a report message to MOSIS. These test results are used by MOSIS' quality control in vendor evaluation. See page 112 of the Reference Section for a sample report to MOSIS. 4.5. List of MOSIS Requests Following is a list of the MOSIS requests. Note that Section 13.3 of the Reference Section contains templates of these requests, along with special instructions for certain requests. ATTENTION This request brings your message or special project requirement directly to the attention of the MOSIS staff. CANCEL-FABRICATE Request to cancel previously requested fabrication of a project. CANCEL-PROJECT Total withdrawal of a project. DELETE-CIF Deletion of last CIF file submitted for a project. END Termination of all requests in a message. FABRICATE Request to fabricate a project. FOUNDRY This option allows you to choose a specific fabricator. INFORMATION Request for information on MOSIS procedures and documents. LIBRARIES Request for cells and/or documentation from MOSIS libraries. NEW-PROJECT Request for creation of a new project. OPTIONS Yes/No options for sharing a chip and requesting a substrate. If you use the SHARE parameter, your chip will be packaged with other projects and the standard quantity divided by the number of projects (the default is NOSHARE). If you request SUBSTRATE (default is NOSUBTRATE), you are requesting that MOSIS include a subtrate connection on the standard pin for that package. QUANTITY Used only to order MORE than the minimum number of parts (see the sample Price Schedule on page 80 for minimum quantities per technology). REPORT User report on the performance of fabricated project(s). STATUS Request for project status. SUBMIT This request ONLY checks the syntax (validity) of a CIF file. UPDATE Modification of project parameters. 4.5.1. Standard Submissions The standard submission style includes three templates: NEW-PROJECT, SUBMIT, and FABRICATE. It is possible to expedite submission by combining a few steps (One-Step Submission), and it is sometimes necessary to fragment large CIF files (N-Step Submission). These are reviewed in Section 13.3 of the Reference Section. 4.5.2. Avoiding Delays Accurate syntax is very important in avoiding error and delay in project submission and in all communication with MOSIS. Remember also that common network problems can cause your project to be received too late for inclusion on the desired run. DO NOT wait until the last minute to submit your project, since this will increase the probability that you won't make the run. Use the MOSIS mail system to make sure that you have the most up-to-date copies of important documents, e.g., the fabrication schedule. 4.6. For More Information Check Reference Section Section 13.3 of the Reference Section contains sample MOSIS request templates and defines the request parameters and their usage. 5. GDSII and CIF Conventions SUBMITTING YOUR DESIGN TO MOSIS IN GDSII, CIF, OR MEBES 5.1. Introduction MOSIS accepts geometry in either GDSII, CIF or MEBES format on a magnetic tape, or in CIF via online file transmission. MOSIS checks the integrity of your submitted file (e.g., syntax, size and layer names), accepting only the projects that conform to these requirements. MOSIS does NOT currently do design rule checking but may do so at a future date. This chapter reviews GDSII and CIF conventions as they relate to procedures for submitting and checking files including, for GDSII projects, the referencing of MOSIS-supported library cells. Accepted projects are scheduled for the first available run in the requested technology. 5.2. GDSII Conventions Please examine the Project Submission Form if you are submitting a design on magnetic tape. This form MUST accompany your tape when you mail it to MOSIS. A sample form is located in the back pocket of this manual. Upon receipt of your tape, MOSIS puts your file data online and checks the integrity of your file. See Section 5.3.2 of this chapter for possible reasons for file rejection. MOSIS' GDSII Conventions are as follows: - The MOSIS layer numbers for each technology are listed in Chapter 6 (Section 6.6). Other layer numberings are accepted if they are clearly spelled out in the project submission documentation. - Non-fabrication (comment) layers may be present; they are read but ignored. However, we strongly urge that all extra layers be removed before submission. - The entire geometry for a project must reside in a single library file; the submission documentation must indicate the name of the top-level structure that is the project. Multiple projects submitted simultaneously may all reside in the same library and specify separate top-level structures. The inclusion of extraneous structures is strongly discouraged. - NODE and BOX elements are read but ignored. - ELFLAGS, PLEX, and ELKEY modifiers are read but ignored, as are element properties. - TEXT of any width is treated as commentary and is not fabricated, i.e., it is forced to zero width. - Fixed-width PATHs (those whose specified width is less than zero) cannot currently be magnified in the course of structure references. - All referenced structures must be defined either in the file or in the declared supported MOSIS cell library. 5.2.1. GDSII Calls for Standard Cell Libraries A submitted design may reference structures (or "cells") maintained by MOSIS in any one of the supported MOSIS cell libraries. The submission document must indicate the name of that library. A GDSII file references a cell in a MOSIS-supported library via a regular structure reference (SREF or AREF) with no corresponding structure definition in the submitted file. 5.3. CIF Conventions The SUBMIT request asks MOSIS to check the integrity of the transmitted CIF file. Please see Section 5.3.2 for a list of possible reasons for the failure of your project. CIF can be sent directly in a MOSIS request message, or by using the CIF-FTP-PATH request command to send your layout geometry as a single file or in fragments (See Section 13.3.1.8 of the Reference Section). 5.3.1. CIF Constraints Please note that CIF specifications encourage some practices that the MOSIS Service disallows. The following are MOSIS conventions: - Polygons (P) must have at least three points (other than this, arbitrary polygons are accepted). - Wires (W) must have at least one point. - Round Flashes (R) must have a non-zero diameter. - Delete Definition (DD) is not allowed. - Symbols may not be redefined. - Lines are limited to 509 characters of text. - The following ASCII characters are not available as CIF blanks due to internal ("CIF 2.71") conflicts: * [ ] ' . (square brackets, single-quote, period). * User extensions are allowed but ignored. * Wires extend beyond the two extreme endpoints by half the wire-width (`square extensions'). * The comment layer has a name ending with the letter "X" ("CX" for CMOS). All geometry on this layer is read by MOSIS but is totally ignored; however, any syntax error may cause CIF file rejection. * The bonding pad layer is named "XP" in all technologies. This optional layer is discussed in Chapter 9 (Section 9.3.6). 5.3.2. Possible Reasons for File Failure With the CHECK_PROJ process, MOSIS computes the size of the project (the Minimum Bounding Box, or MBB) and counts the pads (for a Nonstandard Frame) or checks the size and location of pads (for a Standard Frame), checking actual with declared values. You will receive either a Pass or a Fail message telling you whether your file is valid. If your file fails, you will receive an error message telling you the specific error(s) found. MOSIS calls these CHECK_PROJ errors. The following is a list of possible CHECK_PROJ errors: - Violation of any of the MOSIS restrictions listed above in Section 5.3.1. - Illegal file syntax. - Reference to a layer name that is not known for the given technology. - Inclusion of any layerless geometry. - Undefined symbol reference. - Gross mis-sizing of the geometry's bounding box; it must be "close" to the project size specified in the submittal requests, i.e., 10 percent or 100 microns in each dimension. - Incorrect pad count. You MUST specify the number of pads in your project in your submittal request. MOSIS must find at least that many pads in the geometry (unless there are zero pads). If MOSIS finds more pads, a warning is issued (unless you specified no pads). MOSIS will NOT reject the CIF, but will use the SPECIFIED count in selecting a package. - Standard frame misfit. If you specify a standard frame, MOSIS must find all the frame's pads at the right places in your project's geometry. - CIF-Checksum error. 5.3.3. CIF-CHECKSUM CIF-CHECKSUM checks the accuracy of message files sent from your computer to MOSIS, either via magnetic tape or over a computer network. To use CIF-CHECKSUM you must run the program on your system and send the values (described below) to MOSIS. MOSIS will then run CIF-CHECKSUM on the received file and verify that the file, as transmitted, is complete. To obtain programs that compute checksum values, send MOSIS an INFORMATION request with the following TOPIC values: - CKSUM1.C (written in 'generic' C, tested on VMS and 4.2 bsd UNIX) - CKSUM1.PAS (written in 'generic' PASCAL, tested on VMS and 4.2 bsd UNIX) - CKSUM1.MAC (written in TOPS-20 assembly) Submit CIF-CHECKSUM as "CHECKSUM: CHECKSUM NCHARS" with two spaces between CHECKSUM and NCHARS. CHECKSUM is computed on the entire file or, if the file is transmitted in smaller fragments, CIF-CHECKSUM should be computed on each fragment. CIF files may undergo several trivial modifications during file transmission - such as replacing EOLs or s by s, addition/deletion of nulls and of trailing spaces, conversion of TABs into SPACEs, and addition of spaces/s at either end of the file. CIF-CHECKSUM is insensitive to these minor changes. CIF-CHECKSUM refers to the actual CIF in that submittal, whether it is an entire CIF file, a single CIF-FRAGMENT, or a CIF-FTP-PATH. CIF-CHECKSUM can be used with the SUBMIT or FABRICATE request. It is optional, but highly recommended, because of the fallibility of electronic mail. When MOSIS receives the file or fragment, if there is a mismatch between MOSIS' computed CHECKSUM and the supplied CHECKSUM, or between MOSIS' computed NCHAR and the supplied NCHAR, the file is rejected. MOSIS will notify the designer. If only one fragment is rejected, MOSIS will retain the rest of the CIF and only that fragment should be resubmitted. 5.3.4. The CIF-FTP-PATH Option Your file can be retrieved by MOSIS using CIF-FTP if your host implements DARPA's IP/TCP/FTP protocol and if it runs an "FTP server". Your file protection must also allow this FTP access. MOSIS will make periodic attempts to retrieve your file and will notify you at the completion of successful transfer or if the transfer attempts fail. If successful, the message you receive from MOSIS will include the CIF-CHECKSUM for your file. If you provide a CIF-CHECKSUM with the CIF-FTP-PATH, MOSIS stores this information for comparison after the file is retrieved. Send an ATTENTION request to MOSIS to obtain instructions on the FTP of CIF fragments. Specifying the CIF-FTP-Path Specify the CIF-FTP-PATH with a one-line parameter of the following form: CIF-FTP-PATH: /hostname/username/password/account/filename hostname the name of an Internet host known to MOSIS. username the name of a user on that host who can login via FTP (if no user name is needed, this field may be left empty). password the literal password needed for the FTP login (may be optional). account the account under which the user needs to login via FTP (this field may be left empty if not required). filename the name of the CIF file. The character "/" may be replaced by any printing character that is not needed in any of the parameter fields. This line may be included in place of the CIF: or CIF-FRAGMENT: line of a SUBMIT or FABRICATE request. The following is an example of the use of this line in a FABRICATE request: --------------------------------------------------------------- | | | | | REQUEST: FABRICATE | | ID: 67890 | | P-P: HELLO THERE | | CIF-FTP-PATH: !HOST.ISI.EDU!DIRECTORY!PASSWORD!!FILE.CIF | | REQUEST: END | | | --------------------------------------------------------------- NOTE: The user chose the field delimiter to be the character "!". No FTP account parameter is required, but the delimiters for the account field are retained. The CIF-FTP-PATH parameters are: your hostname, login directory, password and filename. 5.4. For More Information Hon, Robert W., and Carlo H. Sequin, A Guide to LSI Implementation, Second Edition XEROX Palo Alto Research Center 3333 Coyote Road, Palo Alto, CA 94304 (Chapter 7 contains the official CIF 2.0 specification.) Mead, Carver, and Lyn Conway, Introduction to VLSI Systems. Reading, Mass.: Addison-Wesley, 1980. (Chapter 4 contains an introduction to CIF 2.0.) Stream Format - GDSII Release 5.2, 1985. Calma Company 501 Sycamore Drive Milpitas, Ca 95035 (This manual contains the latest specification of GDSII.) 6. CMOS/Bulk 6.1. Introduction MOSIS works with CMOS/Bulk fabricators capable of supporting 3.0, 2.0, 1.6, and 1.2 micron (feature size) double-metal technologies. The technologies are based upon two sets of design rules. The first set of scalable and generic design rules are for 3.0, 2.0, 1.6, and 1.2 micron double-metal (P well, N well, OR twin tub) processes. The second, nonscalable set is ONLY for 3.0 micron P well (double metal). Magic technology files are available from MOSIS for scalable and nonscalable CMOS. These files control design rule checking and map the Magic layers to or from GDSII or CIF layers. For more details on Magic see Chapter 8, Section 8.3.2.1. 6.2. Scalable CMOS/Bulk MOSIS offers a scalable CMOS/Bulk (SCMOS) process with a second level of metal for interconnection. The main advantage of this technology is that it is scalable from 3.0 to 1.2 microns, since the same set of design rules covers all four feature sizes. This means that a 3.0 micron layout can be fabricated at 2.0, 1.6, or 1.2 microns by scaling a large fraction of the layout instead of redesigning to a new set of design rules. Pads, of course, cannot be scaled. These design rules also handle P well, N well, or twin tub processes. 6.2.1. Magic Technology Files ---------------------------------------------------------------------- | | | | | The MOSIS version of the Magic technology files for SCMOS is | | frequently updated. WE RECOMMEND THAT YOU OBTAIN | | THIS FILE THROUGH MOSIS DIRECTLY. | | | | | ---------------------------------------------------------------------- To obtain this file, contact our MOSIS staff or send an online request message in the following format: REQUEST: INFO TOPIC: SCMOS.Tech REQUEST: END 6.2.2. Specifying Scalable Technologies Specify the technology in the NEW-PROJECT request for your project. The various SCMOS technologies are explained below (double poly is specified as SCPE, SCNE, SCEE and SCGE). TECHNOLOGY: SCP - P well processes (must include P well and P select layers). TECHNOLOGY: SCN - N well processes (must include N well, N select, or P select layers). TECHNOLOGY: SCE - P well or N well, processes (must include both wells and selects). MOSIS ignores N well and N select for a P well run and ignores P well and P select for a N well run. TECHNOLOGY: SCG - P well or N well, (must include a well and a select). MOSIS converts the well and select layers to P well and P select for P well processes and N well and N select for N well processes. TECHNOLOGY: SC*E - Adding E to SC*, e.g., SCPE, specifies the double poly process. 6.2.3. Specifying Lambda The desired value of lambda must also be specified. Note that this is NOT necessarily the grid size used by your CAD system. - LAMBDA: 1.5 for 3.0 micron feature size runs - LAMBDA: 1.0 for 2.0 micron feature size runs - LAMBDA: 0.8 for 1.6 micron feature size runs - LAMBDA: 0.6 for 1.2 micron feature size runs 6.3. P well CMOS/Bulk (3.0 Micron) MOSIS supports a CMOS/Bulk process with a second layer of metal (CBPM) for interconnection. 6.3.1. Magic Technology Files --------------------------------------------------------------------- | | | | | The MOSIS version of the Magic technology files for CMOS is | | frequently updated. WE RECOMMEND THAT YOU OBTAIN | | THIS FILE THROUGH MOSIS DIRECTLY. | | | | | --------------------------------------------------------------------- To obtain this file, contact our MOSIS staff or send an online REQUEST message in the following format: REQUEST: INFO TOPIC: CBPM3u.Tech REQUEST: END Please be sure to specify the technology desired in the NEW-PROJECT request as follows: TECHNOLOGY: CBPM includes second metal and via layers for a second interconnect level. ---------------------------------------- | | | | | LAMBDA: 1.5 | | for 3.0 micron feature size runs | | | | | ---------------------------------------- Projects submitted for fabrication in the CBPM technology which contain no second metal or via features will be rejected at CHECK_PROJ. 6.4. CMOS with Capacitor Option To satisfy the requirements of analog designers, the MOSIS Service has developed a vendor-base capable of supporting a capacitor option, SC*E. BiCMOS and CCD options for CMOS processing are in development. Designers can use the MOSIS scalable set of design rules or the fabricator's own set of rules for these new options. 6.5. Electrical and SPICE Parameters MOSIS places its own test structures on each wafer and checks these structures on its tester. These results are used to confirm that each accepted wafer meets both the fabricator's electrical parameter specifications and MOSIS' specifications. MOSIS then generates SPICE Level 2 and/or BSIM model parameters for each run from these measurements. Sample electrical parameter test results are shown in Section 13.4 of the Reference Section along with sample SPICE Level 2 decks and BSIM. A Level 2 deck is also derived for each 3.0 and 2.0 micron fabrication run; a BSIM deck is derived for each 2.0, 1.6, and 1.2 micron run. MOSIS-provided SPICE model parameters (Level 2) are obtained from transistor DC curve fitting using a parameter optimizer and measurements from selected test structures. The optimizer uses the measured I-V data from fabricated transistors to obtain the SPICE model parameters. Each set of SPICE parameters is used to simulate a set of inverters as well as a ring oscillator. These circuits are fabricated as part of the MOSIS Process Monitor. The simulation of the test circuits is compared with the physical test circuits on the Process Monitor and the results are accurate to within 10 to 20 percent of measured performance. 6.6. Geometry Layers The charts below list the CIF and GDSII layer names that MOSIS accepts. In all technologies, CIF layer XP specifies boxes (NOT polygons) that designate bonding pad sizes and locations. See Chapter 9 (Section 9.3.6) for details. GDS users should note that only the layers listed in these charts are actual GDSII layers. All other layers are treated as comments (i.e., read but ignored); this has been indicated in the charts with an asterisk. Technology CIF GDSII CBPM P well, double level metal with MOSIS 3.0u rules. CW (1) P WELL CD (3) ACTIVE CP (4) POLY CS (5) P+ SELECT CC (7) CONTACT CM (8) METAL1 CV (13) VIA CQ (14) METAL2 CG (9) GLASS CX (*) COMMENT (non-fabricated geometry) SCP P well, double level metal with MOSIS scalable rules. CWP (41) P WELL CAA (43) ACTIVE CSP (44) SELECT CPG (46) POLY CCP (47) CONTACT TO POLY CCA (48) CONTACT TO ACTIVE CMF (49) METAL1 CVA (50) VIA CMS (51) METAL2 COG (52) GLASS CX (*) COMMENT (non-fabricated geometry) SCN N well, double level metal with MOSIS scalable rules. CWN (42) N WELL CAA (43) ACTIVE CSN (45) SELECT CPG (46) POLY CCP (47) CONTACT TO POLY CCA (48) CONTACT TO ACTIVE CMF (49) METAL1 CVA (50) VIA CMS (51) METAL2 COG (52) GLASS CX (*) COMMENT (non-fabricated geometry) Technology CIF GDSII SCG Generic wells, double level metal with MOSIS scalable rules. CWG (53) WELL CAA (43) ACTIVE CSG (54) SELECT CPG (46) POLY CCP (47) CONTACT TO POLY CCA (48) CONTACT TO ACTIVE CMF (49) METAL1 CVA (50) VIA CMS (51) METAL2 COG (52) GLASS CX (*) COMMENT (non-fabricated geometry) SCE Both wells, double level metal with MOSIS scalable rules. CWP (41) P WELL CWN (42) WELL CAA (43) ACTIVE CSP (44) SELECT CSN (45) SELECT CPG (46) POLY CCP (47) CONTACT TO POLY CCA (48) CONTACT TO ACTIVE CMF (49) METAL1 CVA (50) VIA CMS (51) METAL2 COG (52) GLASS CX (*) COMMENT (non-fabricated geometry) SC*E Add the following two layers to the scalable technologies listed above. CEL (56) ELECTRODE CCE (55) CONTACT TO ELECTRODE 6.7. Layout Grids When you are submitting CIF to MOSIS, your design layout should be in centimicrons; NEVER submit a design in lambda or centilambda. 6.7.1. SCMOS Rules - 3.0, 2.0, 1.6, and 1.2 Micron If you are using the MOSIS Scalable and Generic CMOS Design Rules (Revision 6), you must stay on a lambda grid for all layers and a half lambda grid for metals. 6.7.2. Nonscalable Rules, 3.0 Micron The MOSIS 3.0 micron P well CMOS Design Rules (Revision 2) require a one micron grid. 6.7.3. Fabricator's Rules Fabricator's rules are variable; check the fabricator's specifications. 6.8. For More Information Weste, Neil, and Kamran Eshraghian, Principles of CMOS VLSI Design - A Systems Perspective. Reading, Mass.: Addison-Wesley, 1985. (An introductory text on CMOS VLSI design.) Glasser, Lance, and Daniel W. Dobberpuhl, The Design and Analysis of VLSI Circuits. Reading, Mass.: Addison-Wesley, 1985. (An advanced text on CMOS VLSI design.) Kamura, K., and T. Sakurai, "Simple Formulas for Two and Three Dimens Capacitances," IEEE Transactions on Electron Devices, February 1983, pp.183-185. (This article shows commonly used formulas for electronic device measurements.) 7. MOSIS Libraries STANDARD CELLS, PADS, AND OTHER CELLS 7.1. Libraries - General Introduction MOSIS maintains a number of cell libraries, both Supported and Unsupported. In the Supported category, MOSIS distributes the CMOS3 Cell Library (a 3.0 micron standard cell library) and the CMOSN Library (a 2.0 and 1.2 micron standard cell library), both developed by the Department of Defense (DoD). Commercial CAD vendor support is available for the CMOS3 Cell Library and is being developed for the CMOSN Library. Unsupported libraries are contributed to MOSIS from various sources. These usually have no usage history or extensive documentation; some of these libraries represent well-designed systems while others are completely experimental. 7.1.1. Supported Supported libraries are available in both GDSII and CIF format. MOSIS maintains new releases of Supported library cells and documentation, and answers questions on general cell functionality (although not branching into specific applications). Supported libraries have the obvious advantage of a previous track record of usage, that is, operational chips already use these cells. 7.1.2. Unsupported Unsupported libraries generally consist of (unchecked) CIF files. Documentation is available online through the MOSIS mail service, or hardcopy materials can be ordered. MOSIS also maintains a 'Remarks' file, in which users can describe their experience with cells. Please direct all inquiries regarding unsupported libraries to MOSIS in an ATTENTION message. 7.2. Library Interfaces - Online and Offline Access Users can access library documentation and cell files via the MOSIS electronic mail service. However, GDSII files are binary and cannot be transmitted. To obtain general information on MOSIS libraries, send an online REQUEST message in the following format: REQUEST: INFORMATION TOPIC: LIBRARY This information will point you to data on specific libraries, including library and cell documentation and stored geometry for the individual libraries. CIF files can also be transferred to you via our network mail system. 7.2.1. Design Submission If you submit your design in GDSII format, MOSIS will insert the library cells you have referenced; whereas in CIF format, you must include the geometry of the library cells in your project geometry. Most commercial vendors, e.g., Mentor Graphics output in GDSII format. 7.2.2. Updates, New Releases Once installed, cells of a library never change. A new release of cells is handled by adding a new cell library (e.g., a "B" or "C" version) that defines the new cells and references the old library for all of the other cells. The general information you receive when you request information (TOPIC: LIBRARY) contains information on new cell library additions and revisions. 7.2.3. Submitting New Libraries and Remarks To submit a new library, new cells, and/or documentation, send a tape to the MOSIS Service or send an ATTENTION message to MOSIS. To comment on your experience with the MOSIS Libraries, either send MOSIS a message via U.S. mail or send an ATTENTION message. 7.2.4. CAD Vendors Supported libraries are available from selected commercial vendors who have integrated the CMOS3 Cell Library into their design support systems. Mentor Graphics currently supports the MOSIS CMOS3 Cell Library. See Chapter 8, (Section 8.2) for more information on commercial CAD services. The CMOSN cell library is being integrated into commercial CAD systems and will soon be available. 7.2.5. Libraries are Technology Specific ---------------------------------------------------------------- | | | | | Each library is technology-specific and can be used ONLY | | with its stated technology. | | | | | ---------------------------------------------------------------- For example: - Pads for the MOSIS 3.0 micron CMOS Bulk P well double metal (Technology CBPM) process and design rules CANNOT be run on SCMOS projects, which use different design rules. 7.3. MOSIS Libraries 7.3.1. CMOS3REL6 (Supported), CBPM 3.0 Micron Technology The CMOS3 Cell Library contains more than 130 cells, including both logic and I/O pad cells. The cells are designed to the MOSIS 3.0 micron CMOS/Bulk P well double metal (CBPM) nonscalable design rules. Chip designs generated using this library can be fabricated through MOSIS on any MOSIS CBPM wafer fabrication run. The CMOS3 Cell Library family is intended to meet the requirements of moderate speed, moderate density, random logic applications and is designed to a set of layout rules and electrical parameters for performance across the MOSIS multivendor-base. CMOS3 standard cells were designed with the following goals and guidelines: - The cell structure is "double-entry" or "multi-port"; I/O terminals are present on both the top and bottom edges of the cell. - Cells were designed to meet stringent cell-level design requirements. The cell structure, terminal locations, and terminal numbering conventions were defined to be compatible with typical automatic routing programs. - The performance of each cell has been characterized over the extremes of electrical parameters and over a wide range of operating conditions including voltage (3V to 7V), temperature (-55 to 125 degrees C), series load resistance (0 to 10K ohms), and parasitic capacitance (.5 pF to 6 pF for functional cells; 10 pF to 60 pF for output pads). - Neither cell performance nor cell density was totally optimized at the expense of the other. The performance characterization indicates that CMOS3 cells can meet design goals of a 20 MHz system clock rate through three or four levels of logic with two or three fanouts per output at 5V, 125 degrees C, and under worst-case processing conditions. 7.3.2. MIT_CBPM30_PADS (Unsupported), CBPM 3.0 Micron Technology This pad set contains nine pads compatible with several MOSIS Standard Frames: In, Buffered-in, Out, I/O (tristate), TTL-level In and Out, a blank pad, and VDD and GND pads. The VDD and GND pads do not interrupt the second metal pad power rings. All pads are 300x640 microns. Input pads have protection diodes, and the output pads can source/sink 30mA with 25ns delay into 50pF. 7.3.3. MIT_SCP30_PADS (Unsupported), SCP 3.0 Micron Technology This pad set contains 3.0 micron SCMOS versions of eight of the nine pads of the MIT_CBPM30u_PADS library (a TTL-level Out pad is not implemented). Included are In, Buffered-in, Out, I/O (tristate), TTL-level In, a blank pad, and VDD and GND pads. The VDD and GND pads do not interrupt the second metal pad power rings. All pads are 300x640.5 microns (200x427 lambda). Input pads have protection diodes, and the output pads can source/sink 30mA with 25ns delay into 50pF. 7.3.4. Tiny_SCP30_PADS and Tiny_SCP20_PADS (Unsupported) SCP 3.0 and 2.0 Micron Technology These 3.0 and 2.0 micron TinyChip pad sets (Tiny_SCP30_Pads and Tiny_SCP20_Pads) include an I/O (tristate) pad, VDD and GND pads, and a blank pad, as well as two cells for building custom pad frames: a corner and a spacer cell. The 3.0 micron pad set can be used in the MOSIS 28 pin Standard Pad Frame (28PC23x34) and the 2.0 micron pad set can be used in the MOSIS 40 pin Standard Pad Frame (40PC22x22). There are "Stuffed" frames which include preplaced pads available as examples (28PC23x34_Stuffed.CIF and 40PC22x22_Stuffed.CIF). 7.3.5. CMOSNREL1 (Supported), NSCE 2.0 and 1.2 Micron Technology This library is a standard cell 2.0 and 1.2 micron library developed by the Department of Defense. It contains the layout of approximately 50 SSI and 30 MSI cells. Cell functions were designed to be functionally compatible with the DoD's CMOS3 Cell family. The CMOSN Cell Library is designed with its own set of lambda-based design rules (not MOSIS scalable rules), optimized for 1.2 micron geometries, which allow scaling up to 2.0 microns. Cells may be processed in either P well, N well or twin tub processes and project geometry must be specified as NSCP, NSCN or NSCE when submitted for MOSIS fabrication. 7.3.6. STD_FRAMES (Unsupported) This library is for information only and has no library cells. It documents the MOSIS Standard Frame pad locations in two formats: pad location box in CIF format (.CIF) and textual pad center-point listing (.LIST). See Chapter 9 (Section 9.3) for details. 7.4. For More Information To order the CMOS3 Cell Library tape, and the CMOSN Cell Library tape and documentation, contact: Christine Tomovich (Documentation Coordinator) The MOSIS Service USC/Information Sciences Institute 4676 Admiralty Way Marina del Rey, CA 90292-6695 Tel: (213) 822-1511 To order the CMOS3 Cell Library book (ISBN 0201-11257-4) contact: Addison Wesley Publishing Company Jacob Way Reading, Massachusetts 01867 Tel: (617) 944-3700 For more information on commercial CAD systems that support the MOSIS CMOS3 Cell Library, contact: Mentor Graphics 8500 S.W. Creekside Place Beaverton, OR 97005-7191 Tel: (503) 626-7000 8. VLSI CAD Tools 8.1. Introduction There is a wide range of VLSI CAD tools that can be used with MOSIS; these have different capabilites, prices, and sources. Only a subset of these is discussed in this chapter; the first part covers commercial CAD tools and the second reviews available public-domain tools. All ASIC geometry, designed on any of these or other similar CAD tools, is acceptable to MOSIS as long as the design layout is compatible with the sets of design rules that MOSIS supports and is within the range of MOSIS' electrical parameters. 8.2. Commercial VLSI CAD Tools for Use with MOSIS There are several commercial CAD companies that support the CMOS3 Cell Library distributed by MOSIS, e.g., Mentor Graphics. Chip designs generated using these CAD systems can be fabricated on any 3.0 micron CBPM MOSIS wafer run. If you are using any of these systems to do standard cell design, you have two alternatives in submitting your design to MOSIS, depending on whether you are designing in GDSII or CIF format. If you submit your design in GDSII, MOSIS will instantiate the library cells during preparation for fabrication. If you are designing in CIF, you need to order the cell library from MOSIS and add the cells yourself before submitting your design. 8.2.1. Circuit Simulation There are many commercial versions of SPICE (the circuit simulator) which provide better convergence and support, as well as handling larger circuits than regular SPICE. HSPICE is one of these; it is available from Meta-Software. 8.3. Public-Domain VLSI CAD Tools for Use with MOSIS 8.3.1. CMOS3 Cell Library This DoD-developed library can be ordered from MOSIS. It contains more than 130 cells, including both logic and I/O pad cells. The cells are designed to the MOSIS 3.0 micron CMOS/Bulk P well double metal (CBPM) nonscalable design rules. Chip designs generated using this library can be fabricated through MOSIS on any MOSIS CBPM wafer fabrication run. (For a description of this library, see Section 1.3.1.) 8.3.2. Berkeley Design Tools The Berkeley VLSI tools consist of programs that help IC designers in all steps of the design process, from initial design steps to analysis of complete VLSI circuits. These tools were developed in the EECS department of the University of California at Berkeley. New tools, OCT and VEM (a design database manager) have been released to further integrate their VLSI CAD environment. 8.3.2.1. Magic Magic is the backbone of the Berkeley integrated circuit CAD software system. It evolved from Caesar, an earlier VLSI graphical editor. With Magic, designers can paint geometry using a mouse and a graphic display system. While Caesar was a simple "what-you-paint" is "what-you-get" scheme, Magic is an "abstract log" type graphic editor. The layers painted are not the actual mask layers used in fabrication. The actual GDSII or CIF layers are generated by Magic from the abstract layers. For example a poly-to-metal contact is drawn and shown as one layer, but the Magic GDSII (or CIF) writer generates the three layers used in fabrication (poly, metal, and the contact cut between them). Designs done with other design tools may be read into Magic via the CIF or GDSII formats. Make sure the lambda scaling and technology match those in Magic. To successfully read a layout done with other tools into Magic, you need a thorough understanding of how Magic interprets CIF and GDSII. 8.3.3. SPICE SPICE was originally developed at the University of California at Berkeley. Several versions of SPICE are available from the University. The most current are SPICE2g6 (written in FORTRAN) and SPICE3a7 (written in C). Both versions of SPICE will run on various systems running 4.2/4.3 bsd UNIX, as well as on machines running VMS. Both versions are distributed by the University of California, EECS Department. MOSIS provides SPICE (Level 2) model parameters (obtained from wafer measurements) for each fabrication run. MOSIS has supplemented SPICE with BSIM parameters for CMOS 2.0, 1.6, and 1.2 micron runs to obtain better simulation results for short channel devices. 8.3.4. Other Public-Domain Design Tools Many universities have also developed CAD tools to facilitate VLSI designs. Stanford University has software which centers on device simulation and model parameter extraction (e.g., ADLIB/SABLE, PISCES, SUPREM). The University of Washington/Northwest (UW/NW) VLSI Consortium puts out a set of VLSI design tools based on the Berkeley Caesar/Magic tool set. One tool of particular interest is a padframe generator that is compatible with MOSIS' Standard Frames. This consortium also provides other macro generators. The Massachusetts Institute of Technology (MIT) also has a set of design tools (e.g., RSIM). Carnegie-Mellon University (CMU) has a set of CAD tools developed as part of their SRC Research Center for CAD. 8.4. For More Information For more information on commercial CAD vendors that can be used with MOSIS, see Chapter 1 (Section 1.4). For more information about HSPICE, contact: Meta-Software, Inc. 50 Curtner Avenue, Suite 16 Campbell, CA 95008 Tel: (408) 371-5100 For more information on obtaining Berkeley VLSI Tools, including Magic, SPICE, OCT, and VEM, contact: Industrial Liaison Program/Software Distribution 479 Cory Hall Department of EECS University of California Berkeley, CA 94720 Tel: (415) 643-6687 For more information about University of Washington Tools, contact: Northwest Lab for Integrated Systems Department of CS, FR-35 University of Washington Seattle, WA 98195 Tel: (206) 545-3796 For more information about Stanford tools, contact: Office of Technology Licensing Software Distribution Center Stanford University Stanford, CA 94306 Tel: (415) 723-0651 For more information about MIT tools, contact: Massachusetts Institute of Technology VLSI Tools Release Microsystems Research Center Room 39-321 Cambridge, MA 02139 Tel: (617) 253-8138 For more information about CMU's tools, including COSMOS, contact: CMU Research Center for CAD Carnegie-Mellon University Pittsburgh, MA 15213 Tel: (412) 268-3617 9.1. Introduction This chapter covers packaging, bonding, and special requests. The first section, packaging, discusses chip and package sizes, quantities, and turnaround times. In the next section, bonding issues are reviewed, including bonding diagrams, project rotation, and the benefits of using MOSIS Standard Frames. The final section discusses special handling requests for packaging and bonding. 9.2. Packaging - General Information 9.2.1. Package Sizes Your project will be packaged in a 28, 40, or 64 pin DIP (Dual In-line Package) or an 84, 108, or 132 PGA (Pin Grid Array) package. Projects may use either a MOSIS Standard Frame or a user-designed Nonstandard Frame. See Sections 9.3.1 and 9.3.2 for more details. MOSIS chooses the package for your chip according to the number of pads in your design and the size of the chip. A large chip will only fit into the 64 DIP and 84, 108, and 132 PGA packages. MOSIS uses top quality ceramic, cavity-up packages; MOSIS DIPs are side-brazed. MOSIS PACKAGE TYPES PIN COUNT PKG TYPE CAVITY SIZE 28 O.6" DIP .310 X .310" 40 0.6" DIP .310 x .310" 64 0.9" DIP .470 x .470" 84 1.1" PGA .350 x .350" .470 x .470" 108 1.2" PGA .350 x .350" .450 x .450" 132 1.4" PGA .350 x .350" .450 x .450" User-Supplied Packages To supply your own packages and lids, contact the User Liaison or send MOSIS an Attention message; this MUST be done when you first submit your request for a Project-ID. When you send your packages and lids to MOSIS, make sure to provide a bonding diagram, which will be sent to the packager with your wafer lot. A special handling and bonding fee of $25.00 per package is charged for 1.6 and 1.2um runs; packaging is included for 3.0 and 2.0 micron runs and the cost does not change when you provide the packages. MOSIS needs to know what type of package you wish to use (DIP, LCC, or PGA), your Project-ID, the number of pins, and any other special features of the package. If our packagers are equipped to handle the type of package that you have specified, MOSIS will notify you and ask you to ship the parts to us along with a bonding diagram. When selecting the packages, you must allow for a cavity size that will accommodate the chip; 50 extra< microns per side is usually adequate. However, if there is to be a downbond, allow an extra 100 microns on that side. Allow enough time for ordered parts to arrive; MOSIS needs time to check with the packager and to get quotes on the cost. Plan to have the packages to MOSIS no later than 3 weeks after the run closes, or there may be a delay in shipment of your parts. 9.2.2. Full Wafer Runs - Project vs. Chip Size A MOSIS chip has a fixed starting frame plus a payload area for user projects. The MOSIS Standard Frame surrounds the chip perimeter and reserves a horizontal area across the top of the chip for identification markings (including the Run-ID and the two-letter Fab-ID). These identification markings and other overhead (scribe lanes, etc.) cause the user payload area to be 200 to 300 microns smaller than the chip. For example, the MOSIS standard project size of 6900 x 6800 (for a medium chip), plus this overhead, produces a chip that is 7100 microns square. Below are the four standard MOSIS chip sizes. Any project that is larger than this maximum project size requires an oversize chip and is treated as an oversize project. At this time, we cannot guarantee that an oversize project can be fabricated unless specific arrangements are made in advance of the run-closing date. Chip Size in Mils Size in Microns Max Proj.Size 3.0um Tiny 100 x 150 2.540 x 3.811 2.3 x 3.4 2.0um Tiny 100 x 105 2.540 x 2.667 2.22 x 2.25 Small 190 x 280 4826 x 7112 4.6 x 6.8 Medium 280 x 280 7112 x 7112 6.9 x 6.8 Large 320 x 375 8218 x 9779 7.9 x 9.2 Your project will be placed in the smallest chip size that can accommodate it. Projects from the same organization may be grouped in one chip. If the projects are small, up to four projects can be packed on a "multiproject chip". See Section 9.2.5 for more details on this SHARE option. 9.2.3. Stepper Runs Because MOSIS 1.6 and 1.2 micron runs utilize stepper (reticle) technology, they do not use standard chip sizes. Please contact MOSIS to book space on these runs (see the Fabrication Schedule notes on these runs in Section 13.1 of the Reference Section). 9.2.4. Quantities The number of packaged parts you receive from MOSIS depends on the physical size of your project. For example, if your CMOS 2.0 micron project is on a small chip size, you receive 12 parts; on a medium chip, 24 parts; and on a large chip, 32 parts. Additional packaged parts may be requested in increments of 6 or 8 parts (for 3.0 or 2.0 micron runs respectively). These quantities are for full wafer lithography runs only. Projects on 1.6 and 1.2 micron stepper (reticle) runs receive 50 packaged parts (minimum lot). To order more than the standard number of parts, use the parameter QUANTITY in your NEW-PROJECT or ONE-STEP Submission Request. (See the QUANTITY parameter in Chapter 13, Section 13.3.7.1.) 9.2.5. Packing Projects MOSIS users sometimes ask if they can pack projects themselves and send them to MOSIS as a single project, in order to save money. When projects are submitted in this fashion, many of the bonding pads usually reside within the interior of the overall chip and are therefore unreachable by any bonding wires. MOSIS cannot bond all these projects simultaneously. Even though it is conceivable that separate bonding diagrams be provided for each project, it is not cost effective. Since only one project can be bonded at a time, the area taken up by all the other unbonded projects will be entirely wasted, as though each project had been submitted separately in the first place. Please Note: If you do pack projects yourself, MOSIS will send you unpackaged parts if you specify PADS:0 in your NEW-PROJECT request or if you specify that you want unpackaged parts on the Project Submission Form that you submit with your geometry. If you do NOT indicate this, your project will be bonded as if it were a single project, that is, ignoring pads not on the periphery of your chip. You may, however, request that your project be packed with others from the same organization, in which case the number of parts you receive will be split among all the projects on the chip (e.g., if you are sharing a chip with two other projects, each of the three will receive 4 parts). You must indicate in the Project Submission Form that you want this "SHARE" option or, for online users, you must include the SHARE parameter in your NEW-PROJECT request to MOSIS (OPTIONS: SHARE). The default is to receive the full complement of parts (NOSHARE). If you request SHARE and there are no others from your organization who are also choosing this option, your project will be packaged in its own chip and you will be charged for the full complement of parts. On a typical run, some spares of a project may exist. Unpackaged spares are shipped with packaged parts to your organization's MOSIS liaison (except for TinyChips) and can be packaged if you have a reasonable need. Remember, however, that there is no guarantee that spares will be available. 9.2.6. Rotation MOSIS usually orients your project as it is submitted. If your project fits the chip payload only when shifted ninety degrees counterclockwise, MOSIS will rotate it. To determine if your project has been rotated, look at the bonding diagram that you receive with your packaged part. If the number in the center of the chip is lying on its side, your project has been rotated for better fit. 9.3. Bonding - Nonstandard Frames and MOSIS Standard Frames Packagers use bonding diagrams to wire bond from the chip to the package. The bonding diagram shows the chip orientation in the cavity, the down-bond (optional), and how the chip pads are wired to the package pins (or through the bonding fingers). It is labeled with your project name, Fab-ID, and Project-ID, and it notes the number of parts to be bonded. A copy of the bonding diagram is shipped with your parts, whether you are using a Standard or Nonstandard Frame (see the bonding diagram illustration at the end of this chapter). 9.3.1. Standard Frames The MOSIS Service offers Standard Frames that specify bonding pad locations and their minimum sizes. These frames facilitate the entire packaging and bonding process; to use a Standard Frame, you need only supply an overglass opening and a square of metal at each specified location. You do NOT have to connect every pad. Various pad libraries that provide pad cells for use in Standard Frames are available online; see Chapter 1 (Section 1.3). There are many benefits to using Standard Frames. Since bonding in these frames is always the same, packaging is standardized. Test jigs can be set up in advance, because you already know how your part will be bonded. Future revisions and modifications of your design can use the same test jigs. MOSIS' automatic pad routing service, Fusion, only supports routing to the various Standard Frames (see Chapter 12 for a discussion of automatic pad routing services). 9.3.2. Nonstandard Frames If you make no declaration that you are using a Standard Frame (via the STD-FRAME parameter), MOSIS creates an individual bonding map reflecting the actual CIF or GDSII file pad layout of your project. This bonding map is sent to you after chip assembly, along with your packaged parts. 9.3.3. Frame Sizes The chart below shows the official "name" assigned to each frame, e.g., 64P79x92. Frame sizes represent your project payload or design area as well as the package pin count. ----------------------------------------------------------------------------- | | | | | Frame Name | | sq mm 28 40 64 84 108 132 | | | | 7.9x9.2 --- --- 64P79x92 84P79x92 --- --- | | | | 6.9x6.8 --- 40P69x68 64P69x68 84P69x68 --- --- | | | | 4.6x6.8 --- 40P46x68 --- --- --- --- | | | | 4.6x3.4 28P46x34 40P46x34 --- --- --- --- | | | | 2.3x3.4 28PC23x34 --- --- --- --- --- | | | | 2.22 x 2.25 --- 40PC22x22 --- --- --- | | | ----------------------------------------------------------------------------- 9.3.4. Procedures for Using Standard Frames To use a Standard Frame: 1. Determine which frame you want to use. 2. Integrate the frame with your design, i.e., put the pads in the right places. 3. Let MOSIS know which frame you are using. Online files are available to help you decide which frame to use. These files come in two formats. One is a CIF file, which draws the bonding pads and the frame outline and highlights pad #1. The other is a LIST file, which documents the bonding pad centers, one per line. Both may be requested as follows: REQUEST: LIBRARY LIBRARY: STD_FRAMES FILE: 28PC23x34.LIST, 28PC23x34.CIF To let MOSIS know which frame you have chosen, you must specify "STD-FRAME" as a parameter in any of the NEW-PROJECT, SUBMIT, FABRICATE, or UPDATE requests. The argument to STD-FRAME is the frame name, for example, STD-FRAME: 28PC23x34. NOTE: When submitting a Standard Frame, you don't need to specify a PADS or a SIZE parameter. During CHECK_PROJ, MOSIS confirms that your Standard Frame project is no larger than the declared frame size and that all the pads of the frame are in the correct locations. If CHECK_PROJ detects any errors, MOSIS will send you an explanatory message. 9.3.5. Pad Geometry and Placement The minimal acceptable pad geometry for both Nonstandard and Standard Frames is an 88 x 88 micron glass cut box over a 100 x 100 micron metal box. This must be centered at the designated pad location. If the design is in a Standard Frame, a pad may be larger and/or off-center, provided that it completely covers the minimum geometry. 9.3.6. XP Layer The bonding pad layer is named "XP" in all technologies. For a Nonstandard Frame, this optional layer lets you call out only those glass cuts that you want MOSIS to use in bonding your project. This allows you to have probe pads (etc.), which MOSIS will not attempt to bond out. If you are using a Standard Frame, you do not need to highlight its bonding pads for MOSIS. ---------------------------------------------------- | | | | | GEOMETRY ON LAYER XP IS USED SOLELY TO HELP | | GENERATE BONDING DIAGRAMS; IT HAS ABSOLUTELY | | NO INFLUENCE ON THE FABRICATED CHIP ITSELF! | | | | | ---------------------------------------------------- MOSIS XP and Pad Layer Checks - MOSIS discovers the bonding pads in a project as follows: If there is ANY geometry on layer XP, MOSIS assumes that each rectangle, either a box (B) or a polygon (P), that is at least 70 x 70 microns and within 400 microns of the project edge, represents a bonding pad position. NOTE: This is a change in policy, as the prior code accepted only boxes (B); the inclusion of rectangular polygons has been added for the convenience of users whose tools do not generate boxes. There is no longer any need to hide pads that are either smaller than 70 x 70 microns or in the interior of the chip. - MOSIS currently checks that all declared bonding pads (in layer XP) have a glass cut feature under them. A project without these features will be rejected, and the user will receive the message: "Bonding marks (layer XP) without passivation cuts are not allowed." - If there is NO geometry on layer XP, MOSIS assumes that the distinct boxes (B) (but not polygons) of reasonable size and within 400 microns of the project edge - not overlapping and not touching - on the overglass cut layer represent bonding pad positions. - MOSIS verifies that there is a metal pad under each bonding pad and will reject any project that does not have metal under glass with the error message: "Bonding passivation cuts found without metal pads underneath." - If you use the XP layer, MOSIS will NOT look at your glass cut layer to find your bonding pads. Therefore, be SURE that the geometry on this layer is correct, since the bonding diagram is generated based on these (presumed) bonding pads. - There are two ways to hide pad layer features, such as probe pads, from MOSIS: either add an XP box or polygon to each pad that you want bonded, or cause all non-bonding pad layer features to appear as polygons (P) rather than boxes (B) on the pad layer. The two methods are equally acceptable. 9.3.7. Pad Placement PLEASE NOTE: Pad placement directly affects your yield. Packaged parts that violate the following suggestions are likely to have shorts or other bonding failures. Keep in mind: 1. The number of pads on a side must not exceed the number of bonding fingers along the cavity edge of a package by more than two. Bonding wires should not be at an angle greater than 45 degrees to the chip's axis. The best rule of thumb is to distribute the pads evenly on all four sides. 2. Bonding pads should be placed along the edges of the project, with 200 micron center-to-center spacing. 3. Bonding wires must not cross over any active circuitry or other pads. 9.3.8. Substrates A downbond, also called a substrate connection, is a wire from a bonding finger to the package cavity. This downbond or substrate connects the package cavity to the chip's substrate both physically and electrically (since the substrate is the bottom of the chip). This bonding finger may also be connected (wired) to one of the chip's pads; if it is, then that pad must be used appropriately (e.g., as a VDD pad for P well CMOS). Substrates are optional but may be requested for all frames - Standard and Nonstandard - EXCEPT for TinyChip Standard Frames. - Standard Frames: Standard Frames do NOT have substrate connections except for 84PGA's which have a substrate at pin #10 due to an internal package connection. This pad must be used appropriately. - Nonstandard Frames: MOSIS does NOT put substrate connections unless they are requested. The ONLY exception to this rule is that the 84 PGAs have the substrate connection at pin #10; these connections are internal to the package that MOSIS uses and cannot be changed. 9.4. Turnaround Approximately three days after a run has closed, a status file is created (for example, M11X.STS). This file allows you to keep track of where your project is in the fabrication and packaging process - for example, what date masks were sent out from MOSIS to the wafer fabricator. It also gives you turnaround summaries for each step and, most important, it helps you to anticipate when you can expect your packaged chip! This file is updated daily and can be requested by network users with the INFORMATION request. 9.5. When Packaging is Finished When device packaging is complete, MOSIS will send you assembled chips with information relating to your project: a bonding map, a brief description of the electrical characteristics of this lot, a SPICE and/or BSIM deck, and the DC parametric measurements from your particular wafer lot. 9.5.1. MOSIS Report Form Along with your packaged parts, you will also receive our MOSIS Report Form. Please take the time to fill this out. We want to know whether your parts work and how they perform. We also want to hear about any defects or problems (do they work fast enough? over voltage? etc). This information is very important for our quality control, helping us to evaluate our vendors. 9.5.2. DAR If you are a MOSIS Liaison, you will also receive a Device Acknowledgment Receipt (DAR). YOU MUST RETURN THIS RECEIPT. Check carefully that all of the listed contents have actually been shipped to you and return the DAR in the attached envelope. 9.6. Special Requests Sometimes designers have special requests. MOSIS makes every effort to accommodate individual requests but must make sure that these requests do not inhibit the normal run schedule. To make a special request, send an ATTENTION message to MOSIS. Be sure to include the Project-ID and Fab-ID in these messages. The MOSIS staff will answer every request. The following sections explain some of the most common Special Requests. 9.6.1. Bond-Same-As To request that a project be bonded the same as a previous submittal, include the parameter BOND-SAME-AS in your message: BOND-SAME-AS: 12345 where 12345 is the other project's ID. You may also use this request if you want to bond a Nonstandard design as if it were a Standard Frame. Just use the frame name instead of the Project-ID., e.g., 28Px46x34, as an argument to the BOND-SAME-AS parameter. Of course, any two projects that have the same Standard Frame specifications will automatically be bonded the same. 9.6.2. Bonding of Spares Spares from your wafer run are currently sent to the MOSIS Liaison. MOSIS will bond spares on request. However, there is no guarantee that spares will exist from your run. Turnaround on this request is also not guaranteed, as these parts will have to be included with other orders to the packager. To have spares bonded, send an ATTENTION message to MOSIS and list the Project-ID, the Fab-ID, and the number of parts needed. We will arrange to have them bonded as soon as we receive them from your MOSIS liaison. Spares will be bonded the same as the original project, and the packaging cost will be charged to your account. 9.6.3. No Bonding To request that a part NOT be bonded, specify PADS: 0. If you do not have your design packaged, you will be receiving ALL the parts that were cut and there will be NO spares. 9.6.4. Hermetic Sealing MOSIS parts are sent with the lid taped on the package to allow you to easily remove the tape and test the chip. If you want your part to be hermetically sealed instead, send an ATTENTION message to MOSIS. (This option is not available for TinyChip projects). 9.6.5. Cancellation of Projects If you discover that your project has a design error after it is already in fabrication, send an ATTENTION message to MOSIS. Although it is too late to avoid the cost of fabrication, we can cancel the expensive packaging step. 9.6.6. Refabricating Your Chip To request that your design be refabricated, send a message to ATTENTION, describing the project you wish refabricated, the number of parts needed, and the reasons for the refabrication. NOTE: No project will be refabricated until the original part has been received and tested and a report has been filed. 9.6.7. Oversize Chips At this time, we cannot guarantee that an oversize project can be fabricated unless specific arrangements are made. 10. Quality Control PARAMETRIC TESTING AND KLA 10.1. Introduction Strict quality control is needed for the manufacture of any sophisticated component. In this section, we will discuss the quality control procedures established between MOSIS and its vendors to ensure that our users receive the highest quality parts. 10.2. Mask Quality Control MOSIS requires its mask vendors to do an automated inspection; for example, for full wafer masks, vendors must perform a chip-to-chip (e.g., KLA) defect inspection over a sample region of each mask to meet MOSIS' density requirements. For direct-step reticles, vendors must do a full inspection and repair of the reticle. Critical dimension marks and alignment figures are also included in each chip. A representative sample is measured by the mask vendor and must be found to be within MOSIS-specified tolerances. These marks are also available for users to do their own measurements. 10.3. Lot Acceptance Testing MOSIS has developed a set of Process Monitors (PMs) to select wafers based on parametric measurements. MOSIS does not do any functional testing of users' designs, because of the proprietary nature of the majority of submitted designs as well as the difficulty of setting up probe cards for Nonstandard Frames. MOSIS does, however, provide an interface with outside testing vendors for users who have completed a MOSIS production run (see Chapter FUNCTIONALSCREENING). Before fabrication, MOSIS locates PMs in key positions across the wafer. After a wafer lot has been fabricated, MOSIS tests its PMs and compares the measurements with the individual vendor's published electrical parameter specification. MOSIS accepts only those wafers that meet these established requirements. A PM for a full wafer lithography run occupies a whole chip site; for stepper lithography, it takes up a section of one of the stepper "views". MOSIS' PMs contain the following types of test structures: - variable-size transistors - variable-ratio inverters - layer sheet-resistance and line-width (electrical) structures - contact resistors - capacitance structures - ring oscillator 10.3.1. SPICE/BSIM Results from SPICE or BSIM tests are used to select the wafers that are sent out to be assembled. A lot summary reflecting test results from these selected wafers is sent to the user along with the packaged chips. Transistor I-V data is also collected from the Process Monitors for use in generating SPICE (Level 2) parameters for 3.0 and 2.0 micron runs, or BSIM (Berkeley Short-channel IGFET Model) parameters for 2.0, 1.6, and 1.2 micron runs. 10.4. Packaging Quality Control MOSIS determines the bonding diagrams for packaging based upon chip size and pad count, taking into account any special requests. MOSIS requires that its packaging vendors meet industry visual inspection criteria including checks for metalization defects, scribing and chip defects, bond and wire inspection, and checks for foreign material. 10.5. For More Information Tyree, Vance, MOSIS Parametric Test Summary. The MOSIS Service USC/Information Sciences Institute, 1987. (This document can be ordered from MOSIS.) SPICE2 Implementation of BSIM Electronic Research Lab Memo ERL-M85/42, University of California, Berkeley, May 1985. Jeng, M. C., B. J. Sheu, and P. K. Ko, BSIM Parameter Extraction-Algorithms and User's Guide. Electronic Research Lab Memo ERL-M85/79, University of California, Berkeley, October 1985. Both memos are available from: EECS/ERL Industrial Support Office 497 Cory Hall University of California Berkeley, CA 94720 11. Functional Screening 11.1. Introduction Most integrated circuit designs fabricated through MOSIS are tested by the designer. However, MOSIS does offer functional testing services for small-volume production runs. A MOSIS vendor tests the projects in wafer form, preventing the packaging of bad chips and saving the cost of both packaging and assembly. Testing services for packaged devices are also available. 11.2. Functional Screening 11.2.1. Schlumberger Technologies/ATE Division Test Services Currently, MOSIS offers functional screening on two types of test systems: S20 or S21. Both of these systems require test vector input in the FACTOR TDL (Test Description Language). While a number of commercial simulators output test vectors in the FACTOR format, MOSIS is investigating a tester-independent TDL, called EDIF, and test conversion programs from this TDL to various test systems. 11.2.2. Designer-Supplied Data You must supply the following items to MOSIS to allow the testing vendor to generate a test program: - Test vectors in FACTOR format. - Data sheet for the project (including Vih, Vil, Voh, Vol, pin assignment, special considerations, etc.). - Probe card 11.2.3. S20 Tester This test system offers test rates of up to 20 MHz, with pin counts of up to 60 pins (59 I/O channels, 1 high-voltage input only). Each input can go from -1 to +6V. The maximum test vector depth is 4,096 vectors at 20MHz without reloading of high-speed vector memory. There are 6 input timing generators, each with 16 timing sets selectable on the fly; and 2 strobe timing generators, also with 16 timing sets selectable on the fly. In addition, there are 3 +/-40V at 1A bias supplies. 11.2.4. S21 Tester This test system offers test rates of up to 20 MHz, with pin counts of up to 120 pins (120 I/O channels). Each input can go from -1 to +6V. The maximum test vector depth is 65,536 vectors at 20MHz without reloading of high-speed vector memory. There are 12 input timing generators, each with 16 timing sets selectable on the fly; and 4 strobe timing generators, also with 16 timing sets selectable on the fly. In addition, there are 3 +/-40V at 1A and 3 +/-10V at 5A bias supplies. 11.3. For More Information S20 Product Description, 1983. Schlumberger Technologies/ATE Division. S21 Product Description, 1985. Schlumberger Technologies/ATE Division. To order either of the above documents, contact: Schlumberger Technologies/ATE Division 1601 Technology Drive San Jose, CA 95115 12. Fusion - Placement and Routing 12.1. Introduction MOSIS is now offering its users a new placement and routing service called the Fusion Service. "Fusion" refers to the automatic placement and wiring of layout cells, which yields a totally integrated, or "fused" layout. This layout may include pads. Variable-sized cells are accepted, and automatic floor planning (e.g., packing) may also be requested. Fusion is a natural extension of the MOSIS Service. It facilitates prototyping by enabling you to test sets of layout cells without investing the enormous effort required to place and interconnect each set, and to place each within a frame of pads. The Service allows you to specify your own leaf cells, accepts variable-sized layout cells, and always provides 100 percent of the wiring. 12.2. CIF Interface The current interface to the Fusion Service is in CIF format. Refer to Chapter 5 (Section 5.3) for more details on CIF conventions. 12.3. CIF to MOSIS When you supply MOSIS with a Fusion specification, you will receive a pair of CIF files. One contains the wiring, and the other contains calls to your leaf cells with the appropriate transformations that place them correctly within the wiring. The CIF files you receive from MOSIS are then appended to your original CIF file (that contains your leaf cells' layouts). You can then submit this concatenated file to MOSIS for fabrication. 12.4. Specifying a Fusion Job There are three considerations in the specification of a Fusion job. First, you must know how to specify a "leaf cell". A leaf cell is one of your layouts, together with information regarding where the "ports" of communication reside along the edges of your layout. If you are a Magic user, we can supply you with programs that will turn Magic cells with labels (for ports) into correctly specified leaf cells. Second, you may want to specify combinations of leaf cells, meant to be wired together. Such specification involves references to leaf cells along with wiring needs. Finally, you may specify that pads be placed around your entire project. This description needs to include a MOSIS Standard Frame name, a pad-library name, an individual specification for each pad, and pinout information (optional). 12.5. Submitting a Fusion Job To receive the MOSIS Fusion document, which includes information on how to submit your job, send a message to MOSIS with the following format: REQUEST: INFORMATION TOPIC: FUSION REQUEST: END If you are not on an electronic mail network, this document can be mailed to you. 12.6. Preparing Your Fusion Job The following steps specify a Fusion job: 1. Prepare Fusion Specification and CIF file. 2. Send Fusion Specification to MOSIS. 3. Append MOSIS' Fusion result to your CIF file in the order shown. 12.7. For More Information Ayres, Dr. Ronald, Fusion: A New MOSIS Service, 1987. USC/Information Sciences Institute, TM-87-194. To order this document, contact: Document Distribution USC/Information Sciences Institute 4676 Admiralty Way Marina del Rey, CA 90292-6695 Tel: (213) 822-1511 13. Reference Section This section contains samples of MOSIS administrative forms, schedules, request message templates, and messages, as well as more technical documents such as SPICE decks and electrical parameters. Many of these forms are periodically updated. ***PLEASE NOTE: Since it is important that you have current copies of these sample forms, MOSIS has the most recent versions online. Hard copies can also be mailed to you upon request. Copies of the MOSIS Customer Agreement Form and applications for DARPA and NSF sponsored use should be requested directly from the MOSIS staff (see Chapter 2, Section 2.4). Design rules, the Offline Submission Form, and sample bonding diagrams are in the back pocket of this manual. Reference Section Contents: Section 13.1 What is MOSIS? includes MOSIS price and fabrication schedules, a list of MOSIS subcontractors and a list of available MOSIS documents. Section 13.2 Getting Started contains a sample MOSIS Customer Agreement Form. Section 13.3 Communicating with MOSIS contains MOSIS Command Language Templates, sample messages to and from MOSIS and MOSIS Command Language parameters. Section 13.4 Designing Your Chip contains SPICE decks and electrical parameters. Section 13.5 MOSIS Glossary contains definitions of many of the terms used in this manual. 13.1. What is MOSIS? - General Information MOSIS SERVICE PRICE SCHEDULE (SAMPLE) (Prices valid through June 30, 1988) Maximum Project Minimum Total Additional Technology Size (mm) Quantities Price 6 Parts ----------------------------------------------------------------------- CMOS 2.3 x 3.4 4 $ 400 N/A 3.0u 4.6 x 6.8 12 $3,500 $ 830 6.9 x 6.8 18 $6,000 $1,130 7.9 x 9.2 24 $10,400 $1,670 ---------------------------------------------------------------------- Technology Price Per Minimum Packaging Sq. mm Lot Cost per Lot ---------------------------------------------------------------------- *CMOS $140/sq. mm 30 $900 2.0u 1.6u $610/sq. mm 50 $1,500 ---------------------------------------------------------------------- Project Size: MOSIS will add scribe lanes and other overhead to the submitted geometry for all technologies; the maximum project sizes listed above refer to actual design area. Packaging: Packaging is included in the 3.0u prices, but the 2.0 and 1.6u feature sizes are priced at $900 for 30 packaged parts and $1500 for 50 packaged parts, respectively. If you wish to use your own packages, send them to MOSIS with a bonding diagram; this diagram will be sent to the packager along with your chips. A sample bonding diagram is provided in this package. When you provide the packages for your designs, there is a special handling and bonding fee of $20 per package. Standard fabrication quantities are expected, but not guaranteed, to yield working parts after allowing for normal VLSI fabrication defects, provided the submitted design is correct. MOSIS delivers a set of bonded and packaged integrated circuits, containing the design exactly as submitted by the customer. MOSIS checks for correct syntax but does not validate designs. Circuits are either bonded per customer instructions or MOSIS provides a diagram showing how bonding was done. A sample from the lot is visually inspected. *Sample cost: [(4.6 X 6.8) * $140] + $900 = TOTAL COST for 30 parts of one small size project. Wafer Acceptance: Wafers are accepted on the basis of parametric test structure measurements rather than on functional tests on users' projects. Each wafer lot must pass the fabricator's parametric tests and is tested again on MOSIS' test structures to ensure conformance with these requirements. MOSIS provides SPICE parameters which have been extracted from MOSIS' test structures on each wafer lot as well as fabricator's corner SPICE decks. A sample from each lot is visually inspected. Additional Parts and Production Orders: If you wish to order more than the minimum quantity 3.0u CMOS parts, request the desired additional quantity in your initial order. These additional parts must be ordered (and are priced) in increments of six. Orders for an entire wafer lot of a single die type, will be accepted only after a project has been successfully fabricated through MOSIS and tested by the designer. Quotes will be given for each individual job. Placing an Order: To place an order with MOSIS, please fill out two copies of our Customer Agreement Form. Both copies of the agreement should be signed by your authorized representative and returned to MOSIS. We will sign them and return one signed original to you. A 20% price discount is available if your project is part of work performed under a current government contract. To receive this discount, please include the following information on the front of your purchase order: 1) Contract Number, 2) Funding Agency, 3) Program Manager, 4) Contract Expiration Date. This discount, however, is not applicable to TinyChip or the 2.0u and 1.6u technologies. MOSIS needs a purchase order in advance, issued to THE MOSIS SERVICE, USC/INFORMATION SCIENCES INSTITUTE, 4676 ADMIRALTY WAY, MARINA DEL REY, CA 90292-6695, ATTN: KATHLEEN FRY. Please note that MOSIS must have a signed Customer Agreement Form before we can process your purchase order and before we can accept designs in either of the two designated formats. MOSIS will accept designs submitted in one of three ways: 1. CIF VIA ELECTRONIC MAIL, e.g., the Internet. Customers will be designated as authorized MOSIS users when a purchase order has been received and approved. 2. CALMA GDSII, CIF or MEBES FORMAT ON MAGNETIC TAPE. These orders will be processed after a purchase order has been received and approved. A bonding diagram must accompany your tape (along with the Offline Submission Form) unless you are using a MOSIS Standard Frame. If you are using a Standard Frame, indicate the frame name, e.g., 28PC23x34, on the Offline Submission Form. General Information / Orders SAM DELATORRE (213) 822-1511 INTERNET: DELATORRE@MOSIS.EDU Information Packet / Documentation Requests CHRISTINE TOMOVICH (213) 822-1511 INTERNET: TOMOVICH@MOSIS.EDU THE MOSIS SERVICE FABRICATION SCHEDULE (SAMPLE) (February, 1988 - January, 1989) ================================================================== DATE CLOSED CODE FEATURE SIZE TECHNOLOGY ================================================================== THU: FEB 4 D 2.0u CMOS N WELL THU: FEB 11 A 3.0u CMOS P WELL THU: FEB 18 E 1.6u CMOS N WELL THU: FEB 25 A 3.0u CMOS P WELL *** ------------------------------------------------------------------ THU: MAR 3 C 2.0u CMOS P WELL THU: MAR 10 N 3.0u NMOS THU: MAR 17 B 3.0u CMOS P WELL DOUBLE POLY THU: MAR 24 A 3.0u CMOS P WELL *** THU: MAR 31 E 1.6u CMOS N WELL ------------------------------------------------------------------ THU: APR 7 C 2.0u CMOS P WELL *** THU: APR 14 A 3.0u CMOS P WELL *** THU: APR 21 D 2.0u CMOS N WELL THU: APR 28 E 1.6u CMOS N WELL ------------------------------------------------------------------ THU: MAY 5 C 2.0u CMOS P WELL*** THU: MAY 12 A 3.0u CMOS P WELL *** THU: MAY 19 D 2.0u CMOS N WELL THU: MAY 26 E 1.6u CMOS N WELL ------------------------------------------------------------------ THU: JUN 2 C 2.0u CMOS P WELL *** THU: JUN 9 A 3.0u CMOS P WELL *** THU: JUN 16 D 2.0u CMOS N WELL THU: JUN 23 E 1.6u CMOS N WELL THU: JUN 30 C 2.0u CMOS P WELL ** ------------------------------------------------------------------- THU: JUL 7 A 3.0u CMOS P WELL *** THU: JUL 14 D 2.0u CMOS N WELL THU: JUL 21 E 1.6u CMOS N WELL THU: JUL 28 C 2.0u CMOS P WELL *** ------------------------------------------------------------------- THU: AUG 4 A 3.0u CMOS P WELL *** THU: AUG 11 D 2.0u CMOS N WELL THU: AUG 18 E 1.6u CMOS N-WELL THU: AUG 25 C 2.0u CMOS P WELL *** ------------------------------------------------------------------- THU: SEP 1 A 3.0u CMOS P WELL *** THU: SEP 8 D 2.0u CMOS N WELL THU: SEP 15 - - - - - - -No run closing - - - - - - - - - THU: SEP 22 C 2.0u CMOS P WELL *** THU: SEP 29 E 1.6u CMOS N WELL ------------------------------------------------------------------- THU: OCT 6 D 2.0u CMOS N WELL THU: OCT 13 A 3.0u CMOS P WELL *** THU: OCT 20 C 2.0u CMOS P WELL *** THU: OCT 27 E 1.6u CMOS N WELL ------------------------------------------------------------------- THU: NOV 3 D 2.0u CMOS N WELL THU: NOV 10 A 3.0u CMOS P WELL *** THU: NOV 17 C 2.0u CMOS P WELL *** THU: NOV 24 E 1.6u CMOS N WELL ------------------------------------------------------------------- THU: DEC 1 D 2.0u CMOS N WELL THU: DEC 8 A 3.0u CMOS P WELL *** THU: DEC 15 C 2.0u CMOS P WELL *** THU: DEC 22 E 1.6u CMOS N WELL THU: DEC 29 D 2.0u CMOS N WELL ------------------------------------------------------------------- THU: JAN 5 A 3.0u CMOS P WELL *** THU: JAN 12 C 2.0u CMOS P WELL *** THU: JAN 19 E 1.6u CMOS N WELL THU: JAN 26 D 2.0u CMOS N WELL =================================================================== *** TinyChips may be submitted to this run. SCHEDULE CHANGES: MOSIS will make every attempt to keep this schedule; however, changes may be unavoidable. For schedule confirmation, send a message to MOSIS@MOSIS.EDU with the following text: REQUEST: INFORMATION TOPIC: SCHEDULE REQUEST: END or contact the MOSIS User Liaison, Sam Delatorre, at (213) 822-1511. PROJECT SUBMISSION: Geometry sent via electronic mail must be received and accepted by MOSIS before 7:00 a.m. on the day the run closes. Geometry on magnetic tape must be received and accepted by MOSIS at least 48 hours before the run closes. Please allow plenty of time when you submit a project; MOSIS cannot hold up a run for late designs. ONLINE USERS: Please check the following 'TABLE OF TECHNOLOGY CODES' for the MOSIS technologies that are acceptable on a given run. For TinyChip runs, you MUST indicate that your technology is either "TINY-SCP" (scalable) or "TINY-CBPM" (non-scalable). You must also put in a 'STD-FRAME' request for the MOSIS 28PC23x34 Standard Frame (which has bonding pads at specific locations). 1.6 Micron Runs: These runs must be booked in advance; please contact Carl Service at (213) 822-1511 to determine space availability. TABLE OF TECHNOLOGY CODES ======================================================== CODE MOSIS DESIGN TECHNOLOGIES LAMBDA ======================================================== A CBPM none SCP 1.5u SCG 1.5u SCE 1.5u --------------------------------------------------- B CBPE none CBP none --------------------------------------------------- C SCP 1.0u SCG 1.0u SCE 1.0u --------------------------------------------------- D SCN 1.0u SCG 1.0u SCE 1.0u --------------------------------------------------- **E SCN 0.8u SCG 0.8u SCE 0.8u --------------------------------------------------- N NMOS 1.5u and up ======================================================== TECHNOLOGY DESCRIPTIONS 3 Micron CMOS -------------------------------------------------------------------- CBP: CMOS/Bulk P WELL (single metal) CBPM: CMOS/Bulk P WELL (double metal) Adds Via (CV) and Metal 2 (CM2) to CBP CBPE: CMOS/Bulk P WELL (double poly) Adds Electrode (CE) to CBP FEATURE SIZE: 3.0 microns only LAMBDA: none REFERENCES: MOSIS 3.0 Micron P WELL CMOS Design Rules, November 1985 (Revision 2) CMOS3 Cell Library, February 1988, (Release 6); NOTE: The CMOS3 Cell Library is for CBPM only. Scalable CMOS --------------------------------------------------------------------- SCP: Scalable CMOS, P well SCN: Scalable CMOS, N well SCG: Scalable CMOS, Generic well SCE: Scalable CMOS, Either well FEATURE SIZE: 1.6 to 3.0 microns LAMBDA: 0.8 to 1.5 microns REFERENCE: MOSIS Scalable and Generic CMOS Design Rules, February 1988 (Revision 6) MOSIS TOPICS (SAMPLE) CATEGORY TOPIC-NAME TOPIC ------------------------------------------------------------------------- A. GENERAL ANNOUNCEMENTS Copies of current MOSIS announcements (also sent to MOSIS liaisons). DIRECTORY Information files currently available through the INFORMATION request (updated daily). GENERAL What the service provides and how to obtain authorization. NETADR Internet address/mail issues. PRICE_SCHED Price list for all MOSIS technologies. SCHEDULE Fabrication schedule/design submittal deadlines. SUBCONTRACTORS List of MOSIS subcontractors. TEMPLATES Various MOSIS REQUEST templates (particularly useful to infrequent users). TOPICS This information. USER-MANUAL General information including MOSIS network interaction. B. CIF CHKSUM Optional computation of CIF filesize to guarantee integrity after transfer. CIFFTP How to have MOSIS retrieve your CIF using FTP. CIF271 Differences between CIF 2.0 and MOSIS' variant, CIF 2.71. LAYERS CIF layer names for MOSIS technologies. C. DESIGN RULES MOSIS_BSIM BSIM parameters taken from different MOSIS 2.0 and 1.6 micron runs. MOSIS_SPECS MOSIS' 3.0, 2.0, and 1.6 micron electrical specifications for all CMOS double metal vendors. VENDOR_SPECS Electrical specifications from MOSIS' vendors. VENDOR_SPICE Corner SPICE from MOSIS' fabricators. D. CHIP SIZES AND QUANTITY PARTS CHIP_SIZES Standard chip sizes and fabrication of nonstandard sizes. QUANTITY-PARTS How to request large quantities of one project. E. LIBRARY LIBDIRECTORY Files currently available through the LIBRARY request (updated daily). LIBRARY Introduction to MOSIS cell library. F. PACKAGING AND BONDING BOND Packaging issues and warnings. STD-FRAMES Standard bonding frames specifications. 84PIN-LAYOUT Layout of the MOSIS-supplied 84 pin grid array package. 108PIN-LAYOUT Layout of the 108-pin-grid-array package supplied by MOSIS. 132PIN-LAYOUT Layout of the 132-pin-grid-array package supplied by MOSIS. G. STATUS ALL-RUNS Status of all runs, including those already completely distributed to designers. run.STS Status of the run named "run" (the name of the run (wafer lot) for a particular fabricated device is the first four characters of its "Fab-ID", e.g., "M11X"). STATUS Status of current runs, i.e., those runs not completely distributed to designers. H. TECHNOLOGY FOUNDRY A list of foundries (for those who want their project to be fabricated at a particular foundry). MAGIC Discussion of MAGIC Technology files for SCMOS and CBPM3u. TECHNOLOGY Summarizes the documentation on MOSIS technologies (CMOS/Bulk), and design rules. TinyChip Describes MOSIS' smallest chip size and tells you how to submit projects. I. TESTING FUNCTIONAL-SCREEN Wafer screening for quantity production. PROBE-CARD User information on special probe card ordering. RUN.PRM The electrical parameters for the run named "run" (e.g., M11X). (The name of the run (wafer lot) for a particular fabricated device is the first four characters of its "Fab-ID", e.g., "M11X"). PROCESS-MONITOR Description of MOSIS' process monitor. To request any of the above information, send an Internet message to MOSIS@MOSIS.EDU including the following lines in the body: REQUEST: INFORMATION TOPIC: Topic-name, Topic-name, Topic-name, etc. REQUEST: END where "Topic-name" is one of the names given above. MOSIS will then mail the topic(s) information to the sender of the request. MOSIS SUBCONTRACTORS (SAMPLE) Dupont Photomask Halycon Microelectronics, Inc. Hewlett Packard International Microelectronics Products (IMP) Master Images, Inc. Micro Mask, Inc. National Semiconductor Corp. Norsk Engineering, Inc. Orbit Semiconductor, Inc. Pantronix Corporation Photo Sciences, Inc. Rockwell International United Technologies Microelectronics Center (UTMC) VLSI Technology, Inc. 13.2. Getting Started University of Southern California/Information Sciences Institute MOSIS CUSTOMER AGREEMENT (SAMPLE) This Agreement is made and entered into by and between the University of Southern California, a California corporation, acting through its Information Sciences Institute, located at 4676 Admiralty Way, Marina del Rey, California, 90292-6695 (hereinafter referred to as "USC/ISI"), and: Customer/Organization Department Street Address City, State and Zip Code Area Code and Phone Number (HEREINAFTER referred to as "Customer".) RECITALS WHEREAS, USC/ISI has developed a computerized system to provide integrated circuit fabrication services through third party vendors to commercial users (hereinafter referred to as "MOSIS") and, WHEREAS, Customer desires to enter into this Agreement with USC/ISI for the provision of such services, NOW, THEREFORE, in consideration of the covenants and conditions hereinafter contained, the parties agree as follows: 1. TERM a. Customer shall submit to USC/ISI a purchase order(s) for MOSIS services which shall be subject to written acceptance by USC/ISI and be effective upon such acceptance; such purchase order(s) shall specify the dollar amount of services desired by Customer. 2. SERVICE a. USC/ISI shall utilize the MOSIS service to: (1) check that syntax is correct (but not including design validation) and deliver wafers or a set of bonded and packaged integrated circuits (chips) containing the design as submitted by Customer and (2) provide fabrication of prototype quantities of integrated circuits. b. Circuits shall either be bonded per Customer instructions or Customer shall be provided with a diagram showing how bonding was done. Individual parts shall be inspected but shall not be tested. Spice parameters, which have been extracted from USC/ISI devices on the same run, will be provided to Customer. c. Each fabrication run shall have passed the vendors' quality assurance and shall have been tested to ensure that it has conformed to MOSIS fabrication requirements. Details are technology specific and are available on request. 3. RATES a. Rates shall be as set forth in Attachment A ("Price Schedule"). 4. NO WARRANTIES a. Customer expressly recognizes that the ability of the MOSIS services to provide working parts in a consistent manner is speculative. USC/ISI expressly disclaims any warranty that use of the MOSIS services will provide working or usable parts, and Customer is not relying on any warranty or on any understanding or belief that use of the MOSIS services will provide working or usable parts, and understands and accepts that each fabrication using the MOSIS services provided by USC/ISI shall be on "as is" basis. USC/ISI EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES AND THERE ARE NO WARRANTIES THAT EXTEND BEYOND THE DESCRIPTION ON THE FACE HEREOF. USC/ISI SHALL NOT BE RESPONSIBLE FOR ANY DIRECT, INDIRECT INCIDENTAL OR CONSEQUENTIAL DAMAGES CUSTOMER MAY SUFFER RELATING TO THE USE OF ANY MOSIS FABRICATION. USC/ISI MAKES NO WARRANTIES, EITHER EXPRESS OR IMPLIED, AS TO ANY MATTER WHATSOEVER, INCLUDING WITHOUT LIMITATION, THE CONDITION OF THE FABRICATION, ITS MERCHANTABILITY OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. USC/ISI shall not be liable for, and Customer hereby assumes the risk of, and will release and forever discharge USC/ISI, its agents, officers, and employees, either in their individual capacities or by reason of their relationship to USC/ISI, in respect to any expense, claim, liability, loss or damage (including any incidental or consequential damage) either direct or indirect whether incurred, made or suffered by Customer or by third parties, in connection with or in any way arising out of the furnishing or use of the MOSIS fabrication. In any event, USC/ISI's liability to Customer on any ground shall not exceed a sum equal to the fee paid to USC/ISI by Customer hereunder. 5. CONFIDENTIALITY AND PROPRIETARY RIGHTS a. Both parties recognize that the information exchanged hereunder is of a confidential and proprietary nature. USC/ISI shall maintain all such confidential and proprietary information provided by Customer hereunder in confidence. As this Agreement envisions transfer of such information to third party vendors, USC/ISI agrees that it shall require each such vendor to execute a Nondisclosure Agreement which shall extend to the information provided by Customer and which shall provide for an obligation of confidentiality commensurate with the obligation called for in this Agreement. USC/ISI further agrees that it shall treat Customer's confidential and proprietary information with the same care with which it treats its own confidential and proprietary information. The obligation of confidentiality shall extend for a period of five (5) years from the date of disclosure and, to that extent, shall survive termination of this Agreement. b. Customer recognizes, however, that because of circumstances beyond the direct control of USC/ISI, there may be disclosure of the material to third parties. USC/ISI, however, will not be liable for any negligent disclosure of Customer's material by any USC/ISI employee or agent, or by any third party vendor, except for as otherwise provided for herein. c. Notwithstanding the provisions of paragraph 5 (a), USC/ISI shall not be obligated with respect to any information which: (i) at the time of disclosure has been published or otherwise is in the public domain, (ii) after disclosure is published or otherwise becomes a part of the public domain through no fault of USC/ISI, or (iii) is or has been rightfully disclosed to USC/ISI, by a party that has no obligation to Customer directly or indirectly with respect thereto to the extent that such third party disclosure is received by USC/ISI without an obligation of confidentiality. d. Customer specifically agrees that it shall not disclose any material which may be considered proprietary or confidential material of USC/ISI or of vendors to any third parties. Proprietary material shall include but not be limited to, proprietary vendor information such as yield and parametric data, whether it was provided to Customers or extracted by them. e. Customer shall be furnished with a list of vendors; if Customer wishes, Customer shall have the opportunity to prohibit certain vendors from working on its fabrication. Vendors shall have been provided with a list of Customers and shall also have the opportunity to refuse to work on the fabrications of certain Customers. f. Nothing in this Agreement shall serve to convey to USC/ISI any proprietary rights in any design submitted by Customer pursuant to this Agreement or in any semi-conductor chip fabricated therefrom. All rights, titles and interests in and to designs for integrated circuits submitted by Customer pursuant to this Agreement as well as all mask works fixed or embodied in any semi-conductor chip fabricated pursuant to this Agreement shall belong entirely to Customer to the extent that Customer has such rights, titles and interests prior to submission to USC/ISI. USC/ISI shall not be responsible for securing any form of statutory protection, whether by patent, copyright, registration under the Semi-Conductor Chip Protection Act or otherwise. g. Customer Customer agrees that it would be difficult and impractical, if not impossible to calculate the dollar amount of damages which might result from the disclosure by USC/ISI, or any employee or agent thereof, or by any third party of Customer's thereof, of Customer's confidential and/or proprietary information. CUSTOMER THEREFORE AGREES THAT USC/ISI'S TOTAL LIABILITY FOR SUCH DISCLOSURE SHALL BE LIMITED TO THE AMOUNT PAID BY CUSTOMER TO USC/ISI UNDER THE TERMS OF THIS AGREEMENT AND THAT THIS AMOUNT IS REASONABLE COMPENSATION FOR SUCH DAMAGES. 6. LEGAL EXPENSES a. In the event that legal action is taken by either party to enforce this Agreement, all costs and expenses, including reasonable attorney's fees, incurred by the prevailing party in exercising any of its rights or remedies hereunder or in enforcing any of the terms, conditions or provisions hereof, shall be paid by the other party. 7. SEVERABILITY a. If any part, term or provision of this Agreement shall be held illegal, unenforceable or in conflict with any law of a federal, state or local government having jurisdiction over this Agreement, the validity of the remaining portions or provisions shall not be affected thereby. 8. GOVERNING LAW a. This Agreement shall be construed and enforced according to the laws of the State of California. 9. MISCELLANEOUS a. Customer warrants that the services provided under this Agreement are for the use of Customer, and not for any parent, subsidiary or third party entity. Customer further warrants that it is not acting as an agent for another party in entering into this Agreement. b. Customer hereby discloses all parent or subsidiary organizations with which Customer is associated: c. The parties agree to abide by all applicable federal, state and local laws and regulations which regulate the activities envisioned by this Agreement. d. This Agreement contains all the agreements, representations, and understanding of the parties hereto and supersedes any previous understandings, commitments, or agreements, oral or written. Any modification to this Ageement must be in writing and signed by both parties. IN WITNESS WHEREOF, the parties hereto have set their hand. UNIVERSITY OF SOUTHERN CALIFORNIA INFORMATION SCIENCES INSTITUTE (Customer/Organization) By By LYN HUTTON Senior Vice President, Administration (Please type or print name) (Date) (Date) SP 12/17/87 13.3. Communicating with MOSIS This section contains MOSIS request templates, MOSIS messages, and replies, as well as a list of MOSIS Command Language parameters and their definitions. A complete list of MOSIS requests can be found in Chapter 4 (Section 4.5). 13.3.1. Templates The following templates contain MOSIS requests. Notice that some of the parameters are mandatory, while others are optional (preceded by "!"). To use a template, fill in the mandatory parameters and the desired optional parameters - being sure to remove the "!" in front of the optional parameters. Send the completed template to MOSIS in a net message. Each message to MOSIS may contain several REQUESTs, each of which may contain several parameters used as arguments for the REQUESTs. All REQUEST messages containing CIF must terminate with REQUEST: END. In certain requests, specific parameters must be listed last; these are shown at the end of each template. For those parameters that must appear last, any parameter that appears after them will be included as part of that last parameter (i.e., not as you may have intended). 13.3.1.1. Attention Template ------------------------ | | | REQUEST: ATTENTION | | !ID: | | !P-PASSWORD: | | (Put message here) | | REQUEST: END | | | ------------------------ Enter text of the message to be sent to a member of the MOSIS staff. The ID and P-PASSWORD must be included only in project-specific ATTENTION requests, but not in general ATTENTION requests. All text between "REQUEST: ATTENTION" and the next REQUEST: is sent to an electronic mailbox that is monitored by a MOSIS staff member and redistributed to an appropriate staff member for a response. PLEASE NOTE: The MOSIS software will NOT PARSE any text that appears after a REQUEST: END, since it reads this as the end of a message. Therefore, DO NOT append request messages together without removing any REQUEST: ENDs or MOSIS will read only the first request. See the One-Step Submission template on page 108 for an example of a message with multiple requests. 13.3.1.2. Information Template -------------------------- | | | REQUEST: INFORMATION | | TOPIC: | | !BYTE-LIMIT: | | !LINE-LIMIT: | | REQUEST: END | | | -------------------------- TOPIC: TOPICS will supply a list of available MOSIS documents. If your host machine enforces limits on the size of incoming messages, you may specify BYTE-LIMIT and/or LINE-LIMIT. MOSIS interprets these two parameters as limits in the body of the message(s) that MOSIS sends in response to your messages. Any response that is larger than one or the other limit will be sent to you in as many messages as required. These are REQUEST parameters (NOT message header parameters) and must follow REQUEST. MOSIS uses these limits for its own text without taking into account the "message header" lines required for network mail. If your host machine limit includes message header lines, you should specify limits at least 500 bytes and 10 lines smaller than your host-enforced limits. Note that the TOPIC: parameter, separated by commas, may be repeated within the request, e.g., TOPIC: SCHEDULE, PRICE_SCHED. 13.3.1.3. Library Templates -------------------- | | | REQUEST: INFO | | TOPIC: LIBRARY | | !BYTE-LIMIT: | | !LINE-LIMIT: | | REQUEST: END | | | -------------------- See the comment in the Information Template, above, for a description of BYTE-LIMIT and LINE-LIMIT parameters. Use this template to determine the library name and filename you are interested in: is one of the MOSIS libraries and is the name of a file residing in the indicated cell library. ----------------------------- | | | REQUEST: LIBRARY | | LIBRARY: | | FILE: | | !BYTE-LIMIT: | | !LINE-LIMIT: | | REQUEST: END | | | ----------------------------- Use this template to request specific library files. 13.3.1.4. New-Project Template ------------------------------------------------------ | | | REQUEST: NEW-PROJECT | | D-NAME: | | D-PASSWORD: | | P-NAME: | | P-PASSWORD: | | ACCOUNT: | | DESCRIPTION: | | TECHNOLOGY: | | LAMBDA: | | !NET-ADDRESS: | | !MAILING-ADDRESS: | | !SIZE: | | !SPECIAL-HANDLING: | | !QUANTITY: | | !FOUNDRY: | | !OPTIONS: (SHARE/NOSHARE, SUBSTRATE/NOSUBSTRATE) | | !BOND-SAME-AS: | | !STD-FRAME: | | !PADS: | | !PHONE: | | !PO: | | !COMMENT: | | !ATTENTION: | | REQUEST: END | | | ------------------------------------------------------ The following parameters MUST be included in the NEW-PROJECT template and need NOT be included in subsequent templates: P-NAME, DESCRIPTION, NET-ADDRESS, PHONE, TECHNOLOGY, LAMBDA, SPECIAL-HANDLING, OPTIONAL, BOND-SAME-AS, STD-FRAME, SIZE, PADS. If your project is NOT a Standard Frame, you must include the SIZE or PADS parameters. The PO parameter is mandatory if your project is a commercial project. MOSIS' new accounting format does not require an affiliation parameter; all new account names begin with digits, e.g., 123. ATTENTION may be either a REQUEST or a parameter of other requests. When you use it as a request, only the text between REQUEST: ATTENTION and the next REQUEST: will be forwarded to the MOSIS staff. When you use ATTENTION as a parameter within a REQUEST message, e.g., with a NEW-PROJECT request, the entire message, including NEW-PROJECT parameters and ending at the next REQUEST will be forwarded to MOSIS personnel. Any inclusion of a command word with a colon, e.g., REQUEST:, will be parsed as a keyword command. If you have a question on message syntax and wish to have a template fragment reviewed by the MOSIS staff, it is important to change the colons to semicolons in the text. If you do not make this change, the MOSIS software reads these as real requests and your message, in its entirety, will not reach the MOSIS staff. See the One-Step Submission template on page 108 for an example of a message with multiple requests. 13.3.1.5. Submit Template --------------------- | | | REQUEST: SUBMIT | | ID: | | P-PASSWORD: | | !CIF-FTP-PATH: | | !CIF-CHECKSUM: | | !COMMENT: | | !ATTENTION: | | !CIF: | | !CIF-FRAGMENT: | | REQUEST: END | | | --------------------- Note that some form of CIF must be present, either CIF or CIF-FRAGMENT. CIF-FTP-PATH and CIF-FRAGMENT may be used together. If either CIF or CIF-FRAGMENT appears, it must be the last parameter in the request. This request submits a CIF file, asking MOSIS to compute the size of the project and count the pads (CHECK_PROJ). It can be issued only after your project has been accepted by MOSIS and you have a valid Project-ID. You will receive an initial acknowledgment from MOSIS and a final Pass or Fail notification. Any CIF file that fails CHECK_PROJ is deleted from the MOSIS database. You should therefore resubmit any revised CIF file in complete form. You may use this request many times for correction and revision of CIF before your project is queued for fabrication. Use the CIF-FTP-PATH option to submit extremely large files or to submit file fragments separately. 13.3.1.6. Fabricate Template ------------------------ | | | REQUEST: FABRICATE | | ID: | | P-PASSWORD: | | !CIF-FTP-PATH: | | !CIF-CHECKSUM: | | !COMMENT: | | !ATTENTION: | | !CIF: | | !CIF-FRAGMENT: | | REQUEST: END | | | ------------------------ If either CIF or CIF-FRAGMENT appears, it must be the last parameter in the request. 13.3.1.7. One-Step (New-Project/Fabricate) Submission Template -------------------------------------------------------- | | | REQUEST: NEW-PROJECT | | D-NAME: | | D-PASSWORD: | | P-NAME: | | P-PASSWORD: | | ACCOUNT: | | DESCRIPTION: | | TECHNOLOGY: | | LAMBDA: | | !NET-ADDRESS: | | !MAILING-ADDRESS: | | !SIZE: | | !SPECIAL-HANDLING: | | !QUANTITY: | | !FOUNDRY: | | !OPTIONS: (SHARE/NOSHARE, SUBSTRATE/NOSUBSTRATE) | | !BOND-SAME-AS: | | !STD-FRAME: | | !PADS: | | !PHONE: | | !PO: | | !COMMENT: | | !ATTENTION: | | REQUEST: FABRICATE | | ID:* | | P-PASSWORD: | | CIF: | | REQUEST: END | | | | | -------------------------------------------------------- The One-Step Submission, for those who need to expedite project submission, consists of a single message containing the NEW-PROJECT request followed by the FABRICATE request. Notice that a "*" is used for the Project-ID. The "*" is used as the ID for your project ONLY in this One-Step Submission (because MOSIS has not yet assigned a Project-ID). All further requests regarding this project must include the real ID as assigned by MOSIS. 13.3.1.8. N-Step Submission To send your CIF file to MOSIS in fragments, use the NEW-PROJECT, SUBMIT and FABRICATE requests as described below: 1. Send MOSIS a NEW-PROJECT request to receive your Project-ID. 2. Divide your CIF file into N fragments so that each fragment is small enough to be handled in a single message. 3. Send N message fragments to MOSIS using the SUBMIT request and the CIF-FRAGMENT parameter described below. 4. Send MOSIS the FABRICATE request when all the fragments have been accepted by MOSIS and the CIF has been checked and is valid. Each SUBMIT request should include the same parameters as in the standard procedure except that, instead of the parameter CIF, the parameter CIF-FRAGMENT should be used. The line with this parameter should look like this: "CIF-FRAGMENT: K/N", where N is the total number of fragments in the CIF project file and K is the number of the fragment. The CIF fragment should start on the line following the CIF-FRAGMENT parameter. MOSIS acknowledges the receipt of each fragment. When the full set has been received, MOSIS will append the fragments together and initiate CHECK_PROJ. You may issue the FABRICATE request only after submitting the last fragment. You may use the DELETE-CIF request at any time to terminate the submission of CIF fragments. This is useful when sudden revisions to a project are necessary. Note that DELETE-CIF will delete ALL CIF for that project. An Important Note on Submitting CIF: Any submission of CIF is terminated either explicitly, by the next request (usually, "REQUEST: END"), or implicitly, when the end of the message is reached. The latter termination typically results in the message trailer (e.g., "------" of SNDMSG, a mailer) being appended to the end of the CIF file. This addition is not harmful after the CIF "E" command, which terminates the CIF file; however, such a trailer may be harmful at the end of CIF-FRAGMENTs, which may be in arbitrary positions in the middle of a CIF file. Therefore, all CIF submissions (especially when using CIF-FRAGMENT) should be explicitly terminated "REQUEST: END". 13.3.1.9. Update Template --------------------- | | | REQUEST: UPDATE | | ID: | | P-PASSWORD: | | !P-NAME: | | !DESCRIPTION: | | !NET-ADDRESS: | | !PHONE: | | !COMMENT: | | !ATTENTION: | | REQUEST: END | | | --------------------- 13.3.1.10. Delete-CIF Template ------------------------- | | | REQUEST: DELETE-CIF | | ID: | | P-PASSWORD: | | !COMMENT: | | !ATTENTION: | | REQUEST: END | | | ------------------------- 13.3.1.11. Cancel-Fabricate Template ------------------------------- | | | REQUEST: CANCEL-FABRICATE | | ID: | | P-PASSWORD: | | !ATTENTION: | | !COMMENT: | | REQUEST: END | | | ------------------------------- 13.3.1.12. Cancel-Project Template ----------------------------- | | | REQUEST: CANCEL-PROJECT | | ID: | | P-PASSWORD: | | !COMMENT: | | !ATTENTION: | | REQUEST: END | | | ----------------------------- 13.3.1.13. Status Template --------------------- | | | REQUEST: STATUS | | ID: | | P-PASSWORD: | | !COMMENT: | | !ATTENTION: | | REQUEST: END | | | --------------------- This will give you status on your run before it reaches the fabrication step. To receive information on your project during fabrication, send an INFORMATION request to MOSIS. See the STATUS topic on page 37. 13.3.1.14. Report Template --------------------- | | | REQUEST: REPORT | | ID: | | P-PASSWORD: | | FAB-ID: | | !COMMENT: | | !ATTENTION: | | !P-NAME: | | REPORT: | | REQUEST: END | | | --------------------- It is particularly important that all performance and yield data be reported separately for each fabrication of a project. Each report should clearly identify both the Project-ID and the Fab-ID of the project. Reports should specify the chip site location(s) of each project -- this information helps MOSIS to classify fabrication defects. The site location of each chip can be found in the top right-hand corner of the die when it is viewed under a microscrope. Note that the REPORT parameter, which is mandatory, must be last. 13.3.1.15. Functional-Screen Template -------------------------------- | | | REQUEST: FUNCTIONAL-SCREEN | | ID: | | P-PASSWORD: | | !COMMENT: | | !ATTENTION: | | | -------------------------------- See Chapter 6 for more information. 13.3.2. Sample MOSIS Messages This section contains samples of messages to and from MOSIS. 13.3.2.1. New Project Request ----------------------------------------------------------------- | | | | | To: MOSIS@MOSIS.EDU | | From: Olive@Navy | | Subject: Intent to submit new project | | | | REQUEST: NEW-PROJECT | | D-NAME: Olive | | ACCOUNT: 78Q-675 | | D-PASSWORD: | | NET-ADDRESS: | | MAILING-ADDRESS: Ms. O. Oyl | | OP-9876 | | NAS Poseidon | | Massachusetts 02177 | | P-NAME: VFFT | | P-PASSWORD: Kaziboo | | DESCRIPTION: This is a device to compute a Very Fast | | Fourier Transform of sonar data, which is | | the key to the securityof underwater rafts. | | It works according to the principles described | | in... | | TECHNOLOGY: CMOS | | LAMBDA: 1.5 | | PADS: 24 | | REQUEST: END | | ---- | | | __________________________________________________________________ ------------------------------------------------------------------------ 13.3.3. One-Step Submission Request ------------------------------------------------------------------------ | | | | | REQUEST: NEW-PROJECT | | D-NAME: POOH | | ACCOUNT: VLSI | | D-PASSWORD: honey | | NET-Address: | | MAILING-Addr: | | US Navy | | Annapolis, MD. 23456 | | P-NAME: MULTIPLY 16x20 | | P-PASSWORD: | | DESCRIPTION: | | multiplier for 1's compliment | | arithmetics, using 2-bit at a time... | | LAMBDA: 1.5 | | PADS: 39 | | | | REQUEST: FABRICATE | | ID: * | | P-Password: | | SIZE: 1850 x 3200 | | CIF: | | (LAP281B --- VFFT.CIF); | | l VFFT); | | DS 1 250 10; | | L ND; | | W 20 960,-50 960,100; | | B 60 500 1030,80; | | ...... | | ...... | | E | | REQUEST: END | | --- | | | ----------------------------------------------------------------------- 13.3.4. New Project Acknowledgment ----------------------------------------- | | | To: Olive@Navy | | From: MOSIS@MOSIS.EDU | | Subject: OK New-Project, 12345 VFFT | | ID: 12345 | | P-Name: VFFT | | Status: New project; no valid CIF. | | | ----------------------------------------- 13.3.5. Fabrication Announcement ----------------------------------------------------------------------------- | | | To: Olive@Navy | | From: MOSIS@MOSIS.EDU | | Subject: Being fabricated: 12345 VFFT | | | | Status: Being fabricated. | | Fab-ID: M78BAD1 | | | | The Fab-ID indicates on which die of run M78B (Brutus) the project | | is fabricated. | | | | From now on please obtain status and scheduling information | | concerning this run by using the following MOSIS request: | | | | REQUEST: INFORMATION | | TOPIC: M78B.STS | | REQUEST: END | | | | The MOSIS Service | | | ----------------------------------------------------------------------------- 13.3.6. Project Report to MOSIS --------------------------------------------------------------------- | | | To: MOSIS@MOSIS.EDU | | From: Olive@Navy | | Subject: REPORT on 12345 M79HED1 VFFT | | | | REQUEST: REPORT | | ID: 12345 | | P-Name: VFFT | | Fab-ID: M79HED1 | | P-P: Kaziboo | | REPORT: | | We received 25 bonded devices for this | | project. 23 of them were found to be | | fully operational at 25MHz. | | | | Both defective chips have the same problem, | | and both came from site No. 43. | | REQUEST: END | | | --------------------------------------------------------------------- 13.3.7. MOSIS Command Language Parameters The following is an alphabetical list of MOSIS parameters to be used with MOSIS requests. (See Chapter 4 for a list of MOSIS requests.) All request and parameter names may be abbreviated, as long as no ambiguities result. 13.3.7.1. Available PARAMETERs ACCOUNT <1 line> Identification of the account to be charged for a project. ATTENTION Requests to bring to the attention of the MOSIS staff some special message or project requirement. May be abbreviated as ATTN. Note: ATTENTION may be either a REQUEST or a parameter of other requests. BOND-SAME-AS <1 line> Specifies the need for bonding to duplicate that of an earlier project or Standard Frame. User may supply either the Project-ID or the Fab-ID of the project to be duplicated, or the name of a MOSIS Standard Frame. BYTE-LIMIT Limits the number of bytes in the body of message(s) that MOSIS sends back to users who request information or library file(s). CIF The project design file. Note: The keyword "CIF:" has no arguments but is followed on the next and subsequent lines by the project design itself. Note also that the CIF design must be the last item in the request. Lines that follow the CIF design, but which do not begin with "REQUEST:", will be considered part of the CIF design (e.g., within the SUBMIT request, if "ATTENTION: " is placed following the CIF text, it will be considered part of the CIF, so that the request will not be manually processed). It is strongly recommended that the CIF be explicitly terminated with another request (e.g., REQUEST: END) rather than implicitly, by the end of the message. CIF-CHECKSUM Pair of numbers computed for a CIF file or fragment to help determine the integrity of the received file or fragment. CIF-FRAGMENT Fragment of a CIF file for a project. CIF-FTP-PATH List of parameters needed to FTP a CIF file to MOSIS. Alternative to the CIF parameter. COMMENT Text totally ignored by MOSIS, to be used by the designer for any purpose. DESCRIPTION Specific description of the project. D-NAME <1 line> Name of the MOSIS user submitting the project. D-PASSWORD <1 line> Password given to this user (D-NAME) to authenticate new project requests sent to MOSIS. FOUNDRY <1 line> Name of foundry(ies) acceptable to designer for fabrication share of a project.It is not necessary to use this parameter when specifying a foundry-specific technology since a foundry is already implied, however, you may use this with all other generic design technologies. ID Unique identification of the project -- assigned by MOSIS. LAMBDA Value of lambda (in microns) that applies to this project. Lambda is one-half the minimum feature size and MUST be provided for all scalable technologies, even if your design system does not use lambda internally. LINE-LIMIT Limits the number of lines in the body of message(s) that MOSIS sends back to users who request information or library file(s). MAILING ADDRESS Address for MOSIS to send packaged parts and correspondence. The address should be in exact form for a shipping label and MUST include the actual designer's name and street address of the organization (including mail-stop, etc.). Do not use PO box numbers -- couriers will not accept them. Warning: Do not include ATTN: or ATTENTION: at the beginning of a line in the MAILING-ADDRESS, or MOSIS will interpret it as an ATTENTION parameter. NET-ADDRESS @ {,@} <1 line> Note: MOSIS will send all replies to requests only to above net address(es). It is very important that net address(es) be kept current throughout the lifetime of the project. PADS Number of pads to be bonded for the project. If this parameter is left unspecified, all boxes on the glass layer will be bonded. A pads value of 0 will produce an unbonded, unpackaged chip. Note: This parameter should not be supplied for a Standard Frame project. PHONE <1 line> Telephone number(s) where user(s) can be reached. P-NAME <1 line> Short name for the project, e.g., ADDER or SHIFTER. P-PASSWORD <1 line> Arbitrary password assigned to the project by the user in the NEW-PROJECT request. QUANTITY <1 line> To order more than the standard quantity of parts (see the MOSIS Price List). REPORT User report to MOSIS on the performance of a fabricated project. SHARE <1 line> Yes/No parameter for the OPTIONS request. These should be on one line with the SUBSTRATE/NOSUBSTRATE parameter (if applicable), separated by commas. This requests that you share the standard quantity and the cost of a chip with others from your organization (up to three others, if available). This parameter is for the small chip size only. The default, NOSHARE, means that you are the sole owner of the chip and will receive the standard quantity of parts. SUBSTRATE <1 line> Yes/No parameter for OPTIONS request, to be combined on one line with the SHARE/NOSHARE parameter (if applicable). This parameter requests that your package bonding include a substrate connection on the standard pin for that package. SIZE x Size of the project in microns. This parameter is required before CHECK_PROJ for Nonstandard Frame projects only. SPECIAL-HANDLING Specifies special size, bonding, and shipping requests. STD-FRAME <1 line> Name of a standard pad frame, i.e., one of several bonding pad placements for which MOSIS is able to offer automatic wire-bonding. TECHNOLOGY <1 line> Project technology (one of the known MOSIS fabrication technologies). TOPIC <1 line> Name of the information topic desired. Note: Requesting TOPIC: TOPICS will retrieve a list of all available information topics. 13.4. Designing Your Chip MOSIS PARAMETRIC TEST RESULTS (SAMPLE) ----------------------------- RUN: M77N / NATALIE VENDOR: UTMC TECHNOLOGY: SCP FEATURE SIZE: 2.0um I. INTRODUCTION. This report contains the lot average results obtained by MOSIS from measurements of the MOSIS test structures on the selected wafers of this fabrication lot. The SPICE and/or BSIM parameters obtained from similiar measurements on these wafers are also attached. COMMENTS: This is MOSIS' first 2um run with UTMC (United Technologies Microelectronics). We would very appreciate your feedback on this run. II. TRANSISTOR PARAMETERS: W/L N-CHANNEL P-CHANNEL UNITS ------------------------------------------------------------------------------ Vth 3/2 1.005 -.954 V Vth 18/2 .970 -.918 V Idss 18/2 2792.0 -1380.0 uA Vpt 18/2 15.00 -15.08 V Vth 50/50 .963 -.908 V Vbkd 50/50 15.0 -16.4 V Kp 50/50 32.9 13.67 uA/V**2 Gamma 50/50 .680 .420 V**0.5 (2.5v,5.0v) Delta Length .057 .029 um Delta Width .423 .381 um COMMENTS: These parameters appear normal. III. FIELD OXIDE TRANSISTOR SOURCE/DRAIN SOURCE/DRAIN PARAMETERS: GATE N + ACTIVE P + ACTIVE UNITS ------------------------------------------------------------------------------ Vth Poly 16.9 -18.0 V Vth Metal1 16.6 -18.0 V Vth Metal2 15.9 -17.9 V COMMENTS: These parameters appear normal. IV. PROCESS N P N P P METAL METAL PARAMETERS: POLY POLY DIFF DIFF WELL 1 2 UNITS ------------------------------------------------------------------------------ Sheet Resistance 29.1 38.9 27.1 44.9 2077.0 .051 .029 Ohm/sq Width Variation -.128 .047 .141 -.341 ---- .267 .073 um (Measured - Drawn) Contact Resist. 17.95 37.61 26.84 27.42 ---- ---- .050 Ohms (Metal1 to Layer) Gate Oxide Thickness: ---- ---- 251. ---- ---- ---- ---- Angst. COMMENTS: These parameters appear normal. V. CAPACITANCE N P METAL METAL PARAMETERS: POLY DIFF DIFF 1 2 UNITS ------------------------------------------------------------------------------ Area Cap .064 .295 .334 .035 .022 fF/um**2 (Layer to subs) Area Cap ---- 1.151 1.102 .053 .033 fF/um**2 (Layer to Poly) Area Cap ---- ---- ---- ---- .031 fF/um**2 (Layer to Metal1) Fringe Cap ---- .455 .475 ---- ---- fF/um (Layer to subs) COMMENTS: These parameters appear normal. VI. CIRCUIT PARAMETERS: ------------------------------------------------------------------------------ Vinv, K = 1 2.11 V Vinv, K = 1.5 2.31 V Vlow, K = 2.0 0.00 V Vhigh, K = 2.0 5.00 V Vinv, K = 2.0 2.45 V Gain, K = 2.0 -19.86 Ring Oscillator Frequency 26.55 MHz (31 stages @ 5.0V) COMMENTS: The ring oscillator frequency is typical for 2um runs. M77N SPICE PARAMETERS .MODEL CMOSN NMOS LEVEL=2 LD=0.030000U TOX=228.00E-10 + NSUB=3.0223E+16 VTO=0.972331 KP=0.000108277 GAMMA=0.661346 + PHI=0.55 UO=714.915 UEXP=0.141544 UCRIT=10000 + DELTA=2.62848 VMAX=53431.5 XJ=0.250000U LAMBDA=0.0132305 + NFS=5.04993E+12 NEFF=0.01001 NSS=1E+12 TPG=1.000000 + RSH=28.070 CGDO=4.54342E-11 CGSO=4.54342E-11 + CJ=0.0002919 MJ=0.494000 CJSW=4.606E-10 MJSW=0.283600 PB=0.750000 * Weff = WDrawn - Delta_W * The suggested Delta_W = 0.109 UM .MODEL CMOSP PMOS LEVEL=2 LD=0.085313U TOX=228.0E-10 + NSUB=6.9452E+15 VTO=-0.856912 KP=2.50608E-05 GAMMA=0.317032 + PHI=0.55 UO=165.469 UEXP=0.335656 UCRIT=203552 + DELTA=3.27661 VMAX=100000 XJ=0.250000U LAMBDA=0.0196736 + NFS=2.65553E+12 NEFF=0.01001 NSS=1E+12 TPG=-1.000000 + RSH=45.92 CGDO=1.29204E-10 CGSO=1.29204E-10 + CJ=0.000334 MJ=0.495300 CJSW=4.92E-10 MJSW=0.239000 PB=0.740000 * Weff = WDrawn - Delta_W * The suggested Delta_W = 0.2876 UM M77N BSIM PARAMETERS NM1 PM1 DU1 DU2 ML1 ML2 *PROCESS=UTMC *RUN=M77N *WAFER=4 *Gate-oxide thickness=228 angstroms *Geometries (W-drawn/L-drawn, units are um/um) of transistors measured were: * 3.0/2.0, 6.0/2.0, 18.0/2.0, 18.0/5.0, 3.0/16.0 *Bias range to perform the extraction (Vdd)=5 volts *DATE=10-7-87 * NMOS PARAMETERS * -1.0053E+000,-6.4243E-002,9.04729E-002 8.26513E-001,0.00000E+000,0.00000E+000 1.31636E+000,1.35871E-001,-8.7925E-002 1.51199E-001,8.07221E-002,-9.1966E-002 -1.4936E-003,2.12922E-003,-1.7172E-003 5.37144E+002,2.99340E-001,6.41267E-001 6.44320E-002,8.65713E-002,-7.3667E-002 -4.7769E-002,5.39781E-001,-9.6250E-003 9.82625E+000,-2.1869E+001,2.07377E+001 -6.6276E-004,-1.2801E-003,-3.7106E-003 2.95373E-004,5.35246E-004,-2.1708E-003 1.38823E-003,-9.4597E-003,8.68428E-003 -9.7408E-003,-2.5987E-002,4.46435E-002 5.42981E+002,2.79306E+002,7.39185E+001 -3.4421E+000,-4.3633E+001,5.72885E+001 -3.8049E+000,6.77103E+001,-7.6340E+000 4.34477E-004,8.63088E-002,-2.3404E-002 2.28000E-002,2.70000E+001,5.00000E+000 2.26670E-010,2.26670E-010,9.71171E-010 1.00000E+000,0.00000E+000,0.00000E+000 1.00000E+000,0.00000E+000,0.00000E+000 0.00000E+000,0.00000E+000,0.00000E+000 0.00000E+000,0.00000E+000,0.00000E+000 * * PMOS PARAMETERS * -2.3390E-001,-1.1873E-002,1.67054E-001 7.12857E-001,0.00000E+000,0.00000E+000 4.73529E-001,-1.4301E-002,-1.8210E-002 5.95367E-003,3.20406E-002,-3.9286E-002 -6.3709E-003,1.63481E-002,2.48801E-003 1.92914E+002,5.45391E-001,7.89169E-001 1.44511E-001,6.63504E-002,-7.7972E-002 -9.4102E-003,1.46722E-001,-2.2863E-002 8.32109E+000,-4.3287E+000,5.79315E+000 -5.6197E-004,-9.8740E-004,-1.2013E-003 7.46256E-004,-7.6068E-004,-1.6059E-003 7.40278E-003,-3.7430E-003,3.22584E-003 -2.2964E-004,6.68204E-004,3.02774E-003 1.96004E+002,6.24674E+001,1.93012E+001 7.46527E+000,-2.0467E+000,7.69066E+000 -2.1625E-002,3.63918E+000,-5.6584E-001 -1.2992E-002,-2.4821E-003,2.03754E-002 2.28000E-002,2.70000E+001,5.00000E+000 4.12989E-010,4.12989E-010,1.19517E-009 1.00000E+000,0.00000E+000,0.00000E+000 1.00000E+000,0.00000E+000,0.00000E+000 0.00000E+000,0.00000E+000,0.00000E+000 0.00000E+000,0.00000E+000,0.00000E+000 * * N+ DIFFUSION LAYER * 28.07, 2.919E-04, 4.581E-10, 1.0E-08, 0.78 0.80, 0.4940, 0.2889, 0.00, 0.00 * * P+ DIFFUSION LAYER * 45.92, 3.340E-04, 4.892E-10, 1.0E-08, 0.74 0.80, 0.4953, 0.2443, 0.00, 0.00 * * METAL LAYER -1 0.051, 2.60E-05, 0.0, 0.0, 0.00 0.0, 0.00 0.00, 0.00, 0.00 * * METAL LAYER -2 0.029, 1.30E-05, 0.00, 0.00, 0.00 0.00, 0.00, 0.00, 0.00, 0.00 13.5. MOSIS Glossary This glossary contains a list of terms and their descriptions as they are used by the MOSIS Service. Some of these terms are standard in the semiconductor industry, while others are specific to MOSIS. Technology names and descriptions (e.g., SCN) can be found in the CMOS chapter. ASIC An acronym for Application Specific Integrated Circuit, e.g., a custom or semi-custom part. BSIM An acronym for "Berkeley Short Channel IGFET Model". A simple and accurate short-channel MOS transistor model, developed at Berkeley, which can be used with SPICE simulation. Bonding fingers Another term for package pins. CHECK_PROJ A step run by MOSIS upon receipt of a GDSII or CIF file to check the validity of the file (syntax, layer names, size, etc.). Projects that do not pass CHECK_PROJ are not accepted. MOSIS does not do any design rule check on submitted files. CIF-CHECKSUM A CIF-specific checksum program designed to ensure the integrity of a CIF file sent from your system to MOSIS. The CIF checksum computed by your system accompanies the CIF file and is compared to the checksum computed by MOSIS on the received file. CIF (Caltech Intermediate Form). A readable text format with specific constructs for describing VLSI circuit(s) layouts. CMOS3 Cell Library A standard cell library developed by a department of the U.S. government and available from MOSIS. DAR An acronym for Device Acknowledgment Receipt. An acknowledgment of receipt of parts from your MOSIS Liaison. Used by MOSIS in tracking and verification procedures. DARPA The Defense Advanced Research Projects Agency provides funding for the MOSIS Service. DIP Dual In-line Package, a rectangular package for integrated circuits with leads along two parallel sides. MOSIS uses 0.6" wide, ceramic, side-brazed packages with 0.1" pin spacing. Downbond Synonymous with substrate connection; a bonding wire from a package bonding finger to the package cavity. Since the die attach used to affix the chip to the cavity is electrically conductive, this connects that bonding finger (and the lead it is connected to) to the substrate of the chip through the package cavity. Electronic mail A text message (mail) sent from one user to another via computer networks. FTP An acronym for File Transfer Program. A software program that allows users to transfer files between computers on the Internet. Fusion Service A placement and routing service; refers to the automatic placement and wiring of layout cells, which yields a totally integrated, or "fused" layout. Gateway A computer that connects networks together. Header Electronic mail messages are divided into text and headers. The header contains address information, e.g., who and where the message is from, and who and where the message is going to; it also includes the date and subject of the message. Lambda: An abstract unit for design layout measurement, which is defined in relation to the fabricator's resolution of the chip-making process. Lambda has different values for different feature size processes and is usually one-half the feature size. Leaf cells A layout with its ports of communication. (See Fusion Service.) Mail relay A host that forwards electronic mail from one network to another. MOSIS Command Language MOSIS automatic message software which allows online users to request information and run status from MOSIS. MOSIS Command Language request A message sent to MOSIS in a "Request" format. All such messages are answered by the automatic message service except "Attention" messages, which are received and answered by the MOSIS staff. NSF The National Science Foundation provides funding for the MOSIS Service. Network A group of connected machines that can transmit information among the different hosts sharing a protocol family, e.g., the Internet uses the IP/TCP protocol suite. Network path The sequence of machine names forming an address path for information flow to and from hosts on other networks. Pad The bonding pad (the square of metal under an overglass opening that the bonding wire is attached to) and the buffer circuitry for input and/or output signals. Payload area The area designated for users' projects on MOSIS' standard chip sizes. MOSIS reserves area for the scribe lanes and the MOSIS labeling strip. PGA Pin Grid Array. A square package for integrated circuits, with leads in a regular grid on the bottom of the package. MOSIS uses cavity-up ceramic packages with 0.1" lead spacing. (Cavity-up means the cavity for the chip is on the top of the package, as with DIPs.) PM Process Monitor. A set of MOSIS' parametric and functional test structures used in wafer lot acceptance. Postmaster The name of the user on your machine who handles undeliverable mail. Probe card A printed circuit board with metal pins that protrude to touch the bonding/probe pads of the DUT (Device Under Test) so that signals can be sent to and received from the part. Project-ID The first request (other than for information) a user sends to MOSIS is for a proposed project. MOSIS replies by assigning a Project-ID (e.g., 12345), which must be used in all future requests pertaining to that project. Protocol A set of communication procedures and formats used between computers on a network (e.g., the IP/TCP suite of protocols on the Internet). Remote network A network that is not directly connected to your machine and therefore must be accessed via a "mail relay". Routing Wiring that causes cells to communicate with one another. Run An aggregation of projects of a particular technology scheduled to be fabricated on the same wafer is referred to as a "run". Site A computer system on a network is called a "site" (also a "node" or "host"). SPICE model parameters These parameters are used to describe the characteristics of a fabrication process (e.g., transistor thresholds). SPICE uses them to determine the behavior of elements as part of a simulated circuit. Standard cells Modular layouts for implementing "common" or "standard" functions. The layouts are usually of a fixed height with fixed power connections; this facilitates automated grouping into rows with routing between the rows. Standard Frame A set of bonding pad locations and their minimum sizes, located around the periphery of a rectangle of fixed size. Substrate See Downbond. TDL Test Description Language; a readable text file with specific constructs for describing test vectors, optional timing, and voltage levels. Test vector The set of voltage levels (0, 1, etc.) to be applied to or received from the DUT (Device Under Test) across the set of DUT pins or pads; also called a test pattern. Your network The group of machines that communicate with your machine using a shared protocol. This group can communicate with other networks via a mail relay.