Subject: Re: MOSIS pads

From: [email-masked] (Paul Cohen)
Date: Mon, 8 Apr 91 13:07:09 -0400

The pads were derived from the MOSIS distributed CIF file using
ciftooct, physically mirrored because mosaico got confused
with the coordinates of 2 cells being the same (I guess it
didn't see the OCT_MIRROR part of the location). 

I'd assume the pads work. I've never actually used them, but
others have, and they've reported success. (I use the m2cframe,
which is bigger, has better drive, etc.)

There were 4 problems with mosaico, all of which still exist.

1) The fact that it didn't notice the mirroring in the 
   translation, which is the reason for the "m" versions of 
   the cells.

2) Mosaico may move the pads a bit, causing them to be in
   the wrong place for fab.

3) It can't deal with the corner cells being in place before
   routing. This is no big deal, since they are just Vdd and GND
   anyway, and can be added later. Just don't forget to add them.

4) Mosaico leaves things off grid if you don't use the compactor,
   sparcs, and if you do use the compactor, it really screws things
   up.

So, what I do is place the core somewhere in the middle of the pad
frame and wire it manually. (This means I could have mirrored things
in the bdnet file, but such is life.)  In Oct 5.0, things get a little
better.  Some of the problems remain, but some get better. I've done
my last few chips with mosaico, and used some new back-end tools to
fix some of the problems. 5.0 will be available soon.

For manual wiring, I suggest the following method. (I can do a 40 pin
chip in under an hour.) All of the following is done with the 
symbolic edting style in Vem.

1) open a small window on the with the whole chip off to the edge 
of the screen. Use the window options menu to set snap to 10 Oct units,
instead of 20. Also open a layer-palette.

2) Open a second window, zoomed in to the terminal on the core you
want to connect to, and a third window zoomed in to the corresponding 
terminal on the I/O pad.

3) Set the path width to 24 lambda for MET1 and MET2 (2 :set-path-width
operations) and connect Vdd and GND. (Do this first so you don't add
additional via resistance to the power supplies).

4) For each terminal on the core, use the pan command to get one
of the zoomed windows centered on each terminal (core and pad), 
then draw a wire from one terminal to the other, using the zoomed windows
to make the actual connections, and the full chip window to get an idea
where you are relative to the "world". (Pan is faster than zoom). 
You'll need to connect to the pads in MET1, and to the core in 
whatever the terminal is on. If you need to cross wires, just
create the wire in whichever layer is more convenient, and use
the :change command to change the layer later. This is faster than
creating a part of the wire and then zooming in to the end so you can 
connect to it.

5) Repeat 4 for all of the signals.

6) Ignore mosaico for now.

Paul B. Cohen 	                            | [email-masked]
Massachusetts Microelectronics Center (M2C) | (508) 870-0312 x244 (V)
75 North Drive	                            | (508) 898-2275      (F)
Westborough, MA 			    |