Jayhawk

University of Kansas

Telecommunications & Information Sciences Laboratory

Electrical Engineering & Computer Science


A Reconfigurable OC-12c and 4-by-OC-3c ATM/SONET Gateway

Faculty
Joseph B. Evans, Gary J. Minden, Victor S. Frost, David W. Petr

Graduate Students
Ben Ewy, Hugo Uriona, Darren Braun, Brian Buchanan, Srini Seetharam, Esmael Yousefi, C. N. Gupta


Abstract

We have designed and implemented a reconfigurable OC-12c and 4 by OC-3c ATM/SONET system based on a set of Xilinx field programmable gate arrays (FPGAs). This design performs the principal transmit and receive functions for an ATM/SONET network interface operating as a single 622 Mb/s OC-12c channel or four independent 155 Mb/s OC-3c channels, including scrambling, descrambling, cell delineation, and overhead mapping. Based on the desired operating mode, the in-system programmable FPGAs which form the core of the design are loaded with the appropriate circuit configurations. Two traffic pacing methods and a statistics collection capability are supported in both of the modes. This implementation is designed for use in the MAGIC gigabit testbed as the basis for an interface between local and wide area ATM networks.

Contents

  • Introduction
  • Gateway
  • Transmit Section
  • Receive Section
  • Conclusion

  • The 622 Mb/s ATM/SONET Gateway Card

    Gateway Photo

    Author

    Joseph B. Evans, <evans@ittc.ku.edu>