University of Kansas

Telecommunications & Information Sciences Laboratory

Electrical Engineering & Computer Science

Switch and Gateway Architecture

Digital AN2 Switch Structure

  • OC-12c/OC-3c links between switches, OC-3c links to hosts
  • crossbar-based switches with 12.8 Gb/s switching capacity
  • scheduled transfers across crossbar, no head-of-line blocking
  • no cell loss, strict credit-based link-by-link flow control
  • routing, connection management drawn from AN1 experience
  • AN2 Switch

    AN2 Line Cards

  • CommonPCB
  • interface to crossbar, crossbar arbitration logic
  • cell buffers (VRAM) and queue management logic
  • line card control processor (LCP) is MIPS R3000; manages address tables, errors, reconfiguration
  • LinkPCB
  • interface to network
  • physical layer dependent functions and optoelectronics
  • KU's Gateway or Digital's multiport card
  • LinkPCB mounts on CommonPCB
  • most custom datapath logic uses Xilinx XC3195 FPGAs
  • Gateway is based on AN2 line card
  • \item switch side is AN2 at 0.8 Gb/s
  • \item network side is ATM/SONET at 622 Mb/s
  • KU Gateway


    Joseph B. Evans, <evans@ittc.ku.edu>