University of Kansas
Telecommunications & Information Sciences Laboratory
Electrical Engineering & Computer Science
Elements of Network Receive Path
Functionality
receives data from SONET/ATM WAN
SONET frame descrambled, overhead stripped
cell stream in SONET payload delineated and descrambled
cell payloads descrambled
cells buffered for rate adaptation
flow control credits updated
cells buffered and addresses mapped on CommonPCB
SONET Descrambler and BIP Verification Chip
byte to word conversion
Section, Line BIP-8 computations and comparisons
SONET descrambling
OC-12c and 4xOC-3c: XC3195-3 @ 20 MHz, 4456 equivalent gates
SONET Path Overhead Termination Chip
tracks and extracts Path Overhead from SONET frame
provides Path Overhead location to other chips
coordinates storage to SRAM for LCP retrieval
computes and verifies Path BIP-8
OC-12c and 4xOC-3c: XC3195-3 @ 20 MHz, 4448 equivalent gates
ATM Cell Delineator Chips
ATM cell delineation (cell stream synchronization)
HEC computation and deletion
cell payload descrambling
idle cell deletion
SONET overhead deletion
4xOC-3c: two XC3195-3 @ 20 MHz, 6300 equivalent gates each
OC-12c: two XC3195-3 @ 20 MHz, 4800 equivalent gates each
Author
Joseph B. Evans
,
<evans@ittc.ku.edu>
