OC-12c Transpose

The Transpose is the second FPGA on the transmit section of the ATM/SONET gateway card. This component is named after the 4xOC-3 version which performs a transpose operation on the four OC-3 streams to byte-interleave them. This document describes the architecture and operation of the OC-12c mode Transpose.

Functional Description

The OC-12c Transpose FPGA the performs the following functions. The Transpose reads the cells stored by the FIFO Controller alternating between two FIFO buffers. These cells consists of thirteen 32-bit words, or 52 bytes only, since the HEC byte is missing. A complete cell is read from one buffer before servicing the second one. After reading four cells the Transpose stops its internal pipeline for one cycle to make up for the four HEC bytes inserted. This event is called a jerk. If there are no cells available for transmission, the Transpose generates idle-cells, i.e. cells with an all-zero header and payload. When it is time to insert SONET overhead, as indicated by the SONET framing signals generated by the FIFO Controller, all the ATM cell processing is stopped for ten clock cycles while the Overhead information is read out of the transmit Overhead SRAM. The Transpose generates the read enables and the column address for this SRAM. The Transpose operates in synchronous cell cycles, similar to the AN2 cell cycles, except that the Transpose cell cycles are interrupted periodically by the insertion of SONET Overhead and by the jerk event. A cell cycle has thirteen SONET word clock cycles (51.44 ns) designated T0 through T12.


A block diagram of the Transpose is shown in Figure 1. All the stages in the data path have enable signals to stop the pipeline during the jerk operation and SONET overhead insertion.

Figure 1: Transpose Architecture

Idle Cell Insertion

This first stage consists of a multiplexer that either passes the data being read from the FIFOs, or generates zeros to insert idle-cells into the cell stream. The select signal is based on the status of the FIFO buffers indicated by their Output Ready flags.

ATM Scrambling

ATM scrambling is required to prevent killer cells from interfering with the correct operation of the equipment. It is used to keep the frequency content of the transmission high. This stage precedes the HEC calculation and insertion modules because the header and the HEC are not scrambled. It is also easier to perform scrambling and this stage because the data still keeps a constant word alignment up to this point. The Transpose implements a 32-bit parallel version of the ATM self-synchronous scrambler, shown in the Figure 2. There is a 43-bit register to keep the state of the scrambler, a logic stage that xors the input data with the first 32 scrambler state bits, and a 32-bit output register. The scrambling operation is disabled at T4 to pass the cell header unmodified. The scrambled bits are fed back to the input of the last 32 bits of the scrambler state register, while the last eleven scrambler state bits are shifted 32 bits forward. The scrambling function can be enabled or disabled by the LCP by toggling the KillATMScramble signal.

Figure 2: Transpose Architecture

HEC Calculation

This module computes the Header Error Control (HEC) CRC byte over the four-byte cell header in parallel. This computation is done in two stages: the first, a combinational logic stage, calculates intermediate terms for each bit in the HEC. The second combines this intermediate terms and stores the final result. The computed HEC is latched at T5 and stored while the header goes through the HEC reservation circuit.

HEC Reservation

This module creates room to insert the HEC byte after the four-byte header of each cell. Logically, it is implemented using three registers: the new and previous registers, which store two consecutive words of a cell, and an output register which is used to format the words making room for the HEC byte. The bytes in the new and previous registers can be shifted when transferred to the output register as shown in Figure 3. The contents of the new register are latched into the previous register in the next cycle, except during a jerk event. The actual implementation inside the FPGA is a little more complex. It uses four copies of the new and previous registers. Each copy has a different physical placement to be able to use the tri-state buffers to multiplex the bytes stored in these registers onto the longlines. There are six possible combinations of byte shifts required which are controlled by a six-bit ring counter with individual enables for each bit. The transition from one state to the next occurs synchronously at a given clock cycle within the cell cycle. The state machine has a 53 cycle period. The state transition diagram for this state machine is shown in Figure 4. In state Shift 0 the four bytes in the new register are transferred to the output register without shifting. The Transpose stays in this state for thirteen clock cycles. The transition from Shift 0 state to Shift 1 state occurs right after a cell header has been latched in the output register. In state Shift 1, the first three bytes of the new register are shifted by one, making room for the last byte from the previous register. The Transpose remains in this state for thirteen clock cycles. The next state, Shift 1-2, is only one cycle long. The first two bytes of the new register are shifted two byte positions. The last byte of the previous register is transferred into the first byte of the output register, while the second byte is left to be replaced by the HEC. The other three states multiplex the bytes as shown in Figure 4. The jerk event occurs at the end of state Shift 3.

Figure 3: HEC reservation

Figure 4: State Transition Diagram

HEC Byte Insertion

This stage comes after the HEC reservation circuit. The input to this module is a cell stream with "holes" to be replaced by the HEC byte. The HEC byte is connected to four different byte-wide registers, since it can be inserted in any of the four bytes within a word. There is a two-bit counter that keeps track of this byte position. This counter is advanced at T7, at the same time the HEC is actually inserted into the ATM cell stream.

Cell Cycle State Machine

This state machine provides timing information to all the modules in the Transpose. It consists of two parts: The first ring counter is stopped by either the jerk signal or the periodic stop signal indicating the insertion of SONET Overhead. The jerk counter is incremented at T12 and the jerk signal is asserted at T1.