ITTC has developed several test vector generation capabilities in conjunction with EDAptive Computing starting with the initial Design Test Vector Generation (DVTG) prototype through VectorGen and the later CART and GENISYS efforts.

DVTG began as an effort to automatically generate test vectors from formal specifications written in VSPEC/VHDL and later migrated to Rosetta. The basic technique involves using static anlaysis techniques to derive test scenarios from a specification, then generating generic test vectors according to user specifications. Finally, concrete vectors are generated in the actual testing langauge.

The CART effort generalized the approach to generating vectors for C++ interface specifiations. The ability to optimize vectors, specify initial conditions, and generate near-false points was added to the original capability. CART also implemented a major update allowing a more modular, parameterized approach to vector generation.

The GENISYS project addressed testing components embedded within a system. Component inversion techniques were developed to back test vectors out to the system interface from the component under test. Component outputs were transformed to generate expected outputs at the system interface. The result is test vectors for testing the embedded component that can be applied and evaulated at the systems interface.