Systems-Level Design Group

The DAPRA ReTarget program has funded work in developing synthesis tools for Software Defined Radios (SDR). Conceptually, ReTarget starts with a radio specifiation written in Rosetta, called a waveform, that is agnostic of implementation fabric. The ReTarget tools synthesize implementations of that waveform in VHDL and C.

The NSF Embedded and Hybrid Systems program has funded work in Systems-Level Design of Embedded Systems. We are specifically concentrating on analyzing interacting cross-cutting system-level requirements to detect emergent behavior in embedded systems.

A SGER project funded by the NSF NeTS program has funded work in Systems-Level Network Design. We are specifically concentrating on analyzing the effects of mobility across networking infrastracture on systems-level security requirements.

The ITTC Technology Transfer program has funded various aspects of Rosetta-related research. Our previous projects helped mature the Rosetta analysis environment to the point where it is now being commercialized by Cadstone, Inc. Current projects examine issues of security in networking systems, specifically looking at analyzing distributed firewall capabilities. This work is commercializing our NSF sponsorted networking research.

The MoBIES effort funded verification of cross-cutting concerns in UML meta-models. The GEM environment was used to generate meta-models that were then integrated to develop domain specific editors. Our project looked at verification of these integrated models.

EDAptive Computing and ITTC teamed on this SBIR effort to generate test vectors for components embedded within systems. Given a set of desired driving values for a component, the GENISYS prototype generates system-level input vectors that generate those values using SAT solving techniques.

EDAptive Computing and ITTC teamed on this SBIR effort to retrieve Rosetta annotated components from a component database using theorem proving techniques. The SPARTACAS prototype, extending earlier work with SOCCER and REBOUND resulted from this effort.

EDAptive Computing and ITTC teamed on this SBIR effort to automatically generate test vectors from Rosetta components.

Intermetrics and ITTC teamed on this effort to develop the original Rosetta specification language. AFRL provided basic research funding that allowed us to pursue the original language definition.

TRW and The University of Cincinnati teamed on this effort to autmomatically generate test vectors from VSPEC and Rosetta specifications. The intent was to use these vectors to verify the fidelity of a new model with respect to an existing component.

The University of Cincinnati HEPE project developed formal techniques and massively parallel simulation techniques for analyzing active networks. The ActiveSPEC and ActiveNodeSPEC systems resulted from this research.

TRW and The University of Cincinnati teamed on this effort to develop simulatable specifications. The UC task was to continue to develop and mature the VSPEC langauge developed during our RASSP effort.

The University of Cincinnati COMET program developed techniques for synthesizing MCM implementations from specifications. Our task was the development of the VSPEC specification language for representing high-level requirements in a manner compatible with VHDL.