facet schmidt_trigger_req(input_voltage:: in real) IS
  begin logic
    req1: test_req(input_voltage, 0.1, 4.9, 0.5);
end;

facet schmidt_trigger(input_voltage:: in real; output_value:: out bit) is
  b :: bit;
begin state_based
  l1: (input_voltage > 0.0) and (input_voltage < 5.0);
  l2: if (input_voltage < 1.0)
        then (b' = 0)
        else (if (input_voltage > 4.0)
                then (b' = 1)
                else (b' = b)
              endif)
      endif;
  l3: (output_value' = b');
end schmidt_trigger;

package test_logic is
begin logic
  test_req(v::real; lbound::number; ubound::number; steps::number)::
      bunch(number) is
           sel( x::number | (lbound =< x) and (x =< ubound) and
                exists( n::natural | x = (n*steps + lbound )));

  export test_req;
end test_logic;