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Programming Models for Hybrid FPGA/CPU Computational Componentshot!

14.01.2004

Andrews, D., Niehaus, D., and Ashenden, P., Programming Models for Hybrid FPGA/CPU Computational Components, IEEE Computer, January 2004.

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Memory Hierarchy for MCSoPC Multithreaded Systemshot!

22.04.2007

Erik Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, and David Andrews, Memory Hierarchy for MCSoPC Multithreaded Systems, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA) June 2007.

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Implementing the Thread Programming Model on Hybrid FPGA/CPU Computational Componentshot!

09.02.2004

Andrews, D., Niehaus, D., Jidin, R., Implementing the Thread Programming Model on Hybrid FPGA/CPU Computational Components, Proceedings of the 1st Workshop on Embedded Processor Architectures (WEPA) held in conjunction with the International Symposium on Computer Architecture, February, 2004, Madrid, Spain.

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Implementing Multi Threaded System Support for Hybrid Computational Componentshot!

26.06.2004

Jidin, R., Andrews, D., Niehaus, D., Implementing Multi Threaded System Support for Hybrid Computational Components, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA), June 2004, Las Vegas, Nevada.

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Impact of Embedded Systems Evolution on RTOS Use and Designhot!

10.04.2005

David Andrews, Iain Bate, Thomas Nolte, Clara M. Otero Perez, Stefan M. Petters, Impact of Embedded Systems Evolution on RTOS Use and Design, Proceedings of the 1st International Workshop Operating System Platforms for Embedded Real-Time Applications (OSPERT'05) in conjunction with the 17th Euromicro International Conference on Real-Time Systems (ECRTS'05), p 13-19, Palma de Mallorca, Balearic Islands, Spain.

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