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Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transformshot!

27.03.2005

R. Jidin, D. Andrews, W. Peck, D. Chirpich, K. Stout, J. Gauch, Evaluation of the Hybrid Multithreading Programming Model using Image Processing Transform, Accepted at 12th Reconfigurable Architectures Workshop (RAW 2005), April 4-5, 2005, Denver, Colorado, USA.

FPGA Implementation of a Priority Scheduler Modulehot!

24.12.2004

J. Agron, D. Andrews, M. Finley, E. Komp, W. Peck, FPGA Implementation of a Priority Scheduler Module, In Proceedings of the 25th IEEE International Real-Time Systems Symposium, Works In Progress Session (RTSS, WIP 2004). Lisbon, Portugal, December 5-8, 2004.

Programming Models for Hybrid FPGA/CPU Computational Componentshot!

14.01.2004

Andrews, D., Niehaus, D., and Ashenden, P., Programming Models for Hybrid FPGA/CPU Computational Components, IEEE Computer, January 2004.

Implementing the Thread Programming Model on Hybrid FPGA/CPU Computational Componentshot!

09.02.2004

Andrews, D., Niehaus, D., Jidin, R., Implementing the Thread Programming Model on Hybrid FPGA/CPU Computational Components, Proceedings of the 1st Workshop on Embedded Processor Architectures (WEPA) held in conjunction with the International Symposium on Computer Architecture, February, 2004, Madrid, Spain.

Impact of Embedded Systems Evolution on RTOS Use and Designhot!

10.04.2005

David Andrews, Iain Bate, Thomas Nolte, Clara M. Otero Perez, Stefan M. Petters, Impact of Embedded Systems Evolution on RTOS Use and Design, Proceedings of the 1st International Workshop Operating System Platforms for Embedded Real-Time Applications (OSPERT'05) in conjunction with the 17th Euromicro International Conference on Real-Time Systems (ECRTS'05), p 13-19, Palma de Mallorca, Balearic Islands, Spain.

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