Until recently radio transmitters and receivers were almost exclusively implemented with analog electronic components. However, a new approach is now becoming popular - one that employs digital electronics to implement most of the analog signal processing functions in the radio. This evolution in radio system design is driven by the ever increasing speed and decreasing cost of microprocessors and high performance analog-to-digital (ADC) and digital-to-analog (DAC) converters. It is no longer uncommon to sample a received signal at the intermediate frequency (IF) stage and process the signal with numerical algorithms using a specialized digital signal processing (DSP) hardware. The DSP hardware performs a variety of operations on the signal including down conversion, demodulation, and filtering; all of which are inherently continuous-time (i.e., analog) processes.

The mathematics of digital signal processing provides the framework for the design of software radio algorithms, while modern high speed digital electronic components make real time implementation of these algorithms possible. However, the hardware currently available to implement DSP algorithms for all stages of the radio system is still limited in speed, accuracy and flexibility. Initially, digital signal processing was used only for baseband waveform processing. As digital electronic devices increased in speed, DSP was soon applied to signal processing functions performed at higher frequencies - e.g., the final IF stage in a radio receiver. Functions such as IF bandpass filtering, automatic gain control (AGC), and coherent modulation and demodulation are typically required at this stage. In the absence of a sufficiently high speed processing capability, innovative techniques such as sub-sampling are used to process bandpass signals of small to moderate bandwidth. This has allowed the boundary between analog and digital processing to be pushed as far up the signal path towards the antenna as permitted by physical electronic devices. For most types of moderate data rate communications - on the order of 100 kB/s or less - bandwidth is not a serious barrier to DSP techniques. However, military radio systems pose a notable challenge because of the wide bandwidth characteristics of spread spectrum modulation.

Military communication systems often require the use of spread spectrum techniques to provide an anti-jam (AJ) capability; or some measure of covertness through the use of low probability of intercept (LPI) waveforms. The result is that extremely wide bandwidth signals are present at the output stage of the transmitter and the input stages of the receiver. We know from the Nyquist theorem and fundamental bandpass sampling techniques that bandpass signals can be sampled at a rate no less than the bandwidth of the signal; so high frequencies alone do not put a limitation on DSP processor capability. However, wide bandwidth signals are a challenge for any type of digital signal processing hardware, and they are especially troublesome for conventional DSP microprocessors. While conventional DSP microprocessors are optimized for real-time data processing, they are nevertheless implemented using the traditional von Neumann architecture - an inherently serial architecture which uses a single multiplier and executes one instruction at a time. While providing the advantage of flexibility through programmability, this architecture limits the speed with which signal samples can be processed. Even modern DSP microprocessors operating at 40 million instructions per second (MIPS) have a useful bandwidth limit of less than 500 kHz. This is especially troublesome for military communication systems which employ AJ and LPI waveforms having typical bandwidths in excess of 10 MHz.

When digital signal processing at wide bandwidths is required the radio designer turns to specialized hardware which can operate at much higher throughputs than is possible with a DSP microprocessor. These include application specific standard products (ASSP), application specific integrated circuits (ASIC), and field programmable gate arrays (FPGA).

Application Specific Standard Products (ASSP) such as FIR filters, correlators, and FFT processors, permit certain popular DSP algorithms or functions to be optimized in hardware at the cost of flexibility. Use of ASSPs can significantly increase the device count and often presents special interface problems which can lead to further complications. Furthermore, due to a narrow range of applicability, many ASSPs may not be available in state of the art process technology [1].

When performance is a factor and product volume is high, many designers turn to ASIC technology. ASIC technology offers the ability to design a custom architecture that is optimized for a particular application. For example a conventional DSP microprocessor has only a single multiply-accumulate (MAC) stage, so each filter tap must be executed sequentially. An ASIC implementation of a DSP algorithm, on the other hand, might have multiple parallel multiply-accumulate (MAC) stages. When comparing the performance of the ASIC versus the DSP microprocessor it becomes apparent that the DSP microprocessor offers slow speed but maximum flexibility (due to programmability) while the ASIC provides high speed with minimal flexibility. Between these two extremes lies the field programmable gate array [2].

Modern field programmable gate arrays can implement functions beyond the capabilities of today's DSP microprocessors. In fact, they have the potential to provide performance increases of an order of magnitude or better over traditional DSP microprocessors, but with the same flexibility [3]. These devices can provide the programmability of software, the high speed of hardware and can be re-configured in-circuit with no physical change to the hardware. In fact, FPGAs are really "soft" hardware, in that they are a good compromise between flexible all-software approaches which unfortunately limit throughput, and custom hardware implementations, which are more expensive and inflexible [4]. FPGAs offer a powerful approach - an architecture tailored to the specific application. Because the logic in an FPGA is flexible and amorphous, a DSP function can be mapped directly to the resources available on the device. Modern FPGAs have sufficient capacity to fit multiple MACs or algorithms into a single device along with the interface circuitry required by the application - a single chip solution.

The essential concept of software radio is that most of the analog signal processing operations of the radio transmitter and receiver are implemented with digital hardware using DSP techniques. The placement of the receiver analog to digital converter (ADC) and the transmitter digital to analog converter (DAC) as close to the antenna as possible are distinguishing characteristics of the software radio. In the software radio receiver, the approach often used is to digitize an entire band and to perform IF processing, baseband, bit stream and other functions completely in software [5]. This approach requires the use of high speed analog to digital converters and high speed DSP microprocessors. However, the signal processing requirements for military and commercial radio systems employing high data rate signals or spread spectrum modulation easily exceeds the processing speeds currently available in off-the-shelf DSP microprocessors. In this case, special purpose DSP hardware, application specific devices and field programmable gate arrays can play an important role.

The motivation for implementing radios in software is that a highly flexible and re-configurable communication system can be implemented for relatively low cost. The ability to adapt the radio to its environment by changing filters, changing modulation schemes, switching channels, using different protocols and dynamically assigning channels and capacity are features which are impractical to deliver with hardware alone. Since the behavior of the software radio can be changed so easily, defining a particular architecture does not limit the radio to one specific function. Instead, multiple radio systems can share a common front-end analog radio tuner while having independent digital processing for each individual radio channel.

A software radio is essentially a hybrid analog and digital processing system. As illustrated in Figure 1, fixed analog filtering and frequency conversion are still used in the RF stages. Conceivably, there will always be a need for an analog low-noise preamplifier to capture the signal from the antenna and establish the noise figure for the receiver. Also, a down-conversion operation which places the signal at some convenient intermediate frequency and allows for additional conditioning of the signal before sampling will probably continue to be a part of the software radio system for the next decade.

Using a sufficiently fast DSP microprocessor, a single device could be used to process the signal through all stages of the communication system. However, the signal processing requirements for each stage are quite different. In the IF stages, relatively simple high speed digital processing is needed, and special purpose DSP hardware can be used to satisfy this requirement. At this stage, signal processing is usually limited to filtering, correlation or FFT processing. At the baseband stage the spread spectrum modulation has been removed and the bandwidth of the signal is much narrower, meaning that fewer samples need to be processed per unit time. However, the complexity of the algorithms required at this stage increases dramatically, and the extra time between samples is required in order to implement digital phase locked loops and other computationally intensive algorithms. Use of simple, high speed DSP processing at the wide bandwidth stages and slower, more flexible processing at the lower bandwidth stages will efficiently satisfy both the complexity and high throughput requirements of modern radio systems [4].

The single most critical requirement in software radio is real-time processing. If the system is to operate in real time, then the data must be moved in and out of the DSP microprocessor on a regular (i.e., sample by sample) basis, where hundreds of instructions may need to be executed for every sample that enters the processor. Obviously, low sample rates are desired for this reason. However, the sample rate requirement is dictated primarily by the information bandwidth of the signal. The information bandwidth in radio systems ranges from under 4 kHz for HF voice band channels to over 1 MHz for cellular systems. Spread spectrum (or CDMA) systems are a notable challenge, especially for military systems where interference excision techniques, or chip wave-shaping (for LPI enhancement), are applied directly to the spread waveform. This requires that complex signal processing be applied at the chip level, which can be one or two orders of magnitude wider bandwidth than the information signal.

A well designed system will use a variety of sampling rates to achieve an efficient flow of data through the processor. At the A/D or the D/A stage, over-sampling is quite often used. Over-sampling of the signal is useful to shift aliases out of band and simplify filtering, so faster sample rates and narrower bandwidths are used. On the other hand, novel under-sampling techniques are possible with stable, linear analog-to-digital converters. Under-sampling techniques can be used to implement bandpass sampling - digitizing the signal in the second or third Nyquist zone, so that the desired signals will be aliased inband by the sampling. Both of these techniques can be combined as needed within the various stages of the software radio to enhance the signal to noise ratio yet maintain the sample rate at the lowest practical level.

When the time between samples is on the order of tens of microseconds to hundreds of nanoseconds such single-sample operations require hundreds of MIPS (million instructions per second) and/or MFLOPS (million floating operations per second) to Giga-FLOPS. A good FIR/IIR channel selection filter could require about 100 operations per sample at 30 Msps, or 3000 MIPS. Using a naive brute force approach, we would require 15 to 60 DSPs cooperating for this section alone, repeated for every channel. As a result, even with faster devices, software on DSPs still cannot be used for the down conversion itself, but must still essentially operate at baseband (albeit a much wider baseband, up to a few MHz). Even the most fundamental demodulation or tuning algorithm requires 10 operations per sample, which would limit a DSP microprocessor to filtering signals with a bandwidth of a few hundred kHz. In a conventional voice-band cellular system, baseband processing requirements can range from 10 to 100 MIPS/MFLOPS per channel; while any digital signal processing at the IF frequency can drive the processing requirements to 500 MIPS/ MFLOPS and upwards of 10 GFLOPS [5].

We contend with these formidable processing challenges by abandoning the use of general purpose processors in favor of a mixed approach in which high speed digital hardware is used in the earliest stages, doing much of the filtering and processing in fast digital logic. When the signal reaches the post-IF stages, the processing load has been reduced considerably so that it can now be effectively handled by general purpose DSP processors. As long as this specialized hardware is versatile and is controllable to some extent from software, a hybrid architecture will meet our requirements. Most IF processing and chip rate processing can be off-loaded to these special purpose devices until the day that general purpose processors with sufficient processing power are available and cost effective.

The most significant limiting factor in development of software radio systems has been the lack of sufficiently fast hardware - most notably, fast DSP microprocessors. As high performance, high speed ADCs have become available commercially, hybrid techniques using specialized digital hardware have become more common, while use of DSP microprocessors has lagged behind. DSPs are getting ever faster, but it will be a while before we can use a single 'ultimate' chip to do everything. Instead, the idea of using multiprocessing to share the effort seems attractive.

Multiprocessing as an alternative to the processing limitations of conventional DSPs can have only limited success. First of all, traditional DSP architectures were not well suited to multiprocessing. In fact, there are only one or two commercially available DSP processors which have the architecture to efficiently support multiprocessing - most notably the Texas Instruments TMS320C40. Also, software to support parallel and multiprocessing is scarce and expensive. Secondly, it is a characteristic of a DSP (as contrasted with a conventional microprocessor) that it must operate on a continuous flow of data. There are few functions in the software radio that could benefit from the power of parallel processors.

Software radios ideally place most IF, and all baseband, bit stream and source processing in a single processor. However, when we examine the speed requirements of the IF stage, especially when spread spectrum is used, we conclude that we need a special purpose device - and this is where FPGAs come into favor. Some of the lower data rate anti-jam tactical communications standards, such as HaveQuick and SINCGARS, are best implemented using high dynamic range software-oriented digital signal processing. In these radios, FPGAs could effectively provide the core of real-time sample rate and baud rate pipelined processing. They could also be used in their more conventional role of providing gate level support for the other processors and ASICs that make up the system.

Recent technical history has suggested that only software and not hardware possesses the programmability that is needed for versatile multi-role radio designs. The flexibility of software is high; but the throughput necessary for any respectable data rate is low, making it suitable only for voice processing data rates. However, the availability of high speed FPGAs provides a greatly enhanced DSP capability which can be reprogrammed to handle wideband digital signal processing tasks. This permits a flexible architecture consisting of dedicated wideband ASICs, FPGAs, and programmable narrowband DSP processors. In the near future, re-configurable modem architectures will provide in excess of 400,000 gates of programmable hardware with throughputs measured in the 100 millions of operations per second and at power consumption levels under 2 watts [4].