Updated final exam topics

I've updated the list of final exam topics on the web page. Basically, what I've covered in class is fair game for the exam. I've listed some chapters from our text for your reference, however topics in those chapters that I did not cover will not be covered on the exam. For example, Chapter 5 discusses caching and virtual memory, but there will be no virtual memory questions on the exam.

New models posted

I've just posted a new set of models for the KURM on the Resources Page. The sign extend components are included and some modifications have been made to the controller and datapath.

Memory issues

Some of you have reported problems with the 2 port memory crashing. The TAs have reported to me that you must initialize inputs to the model when your simulation starts. Specifically, the addresses and read/write strobes. Setting them to 0 is the simplest thing to do.

Controller and datapath update

I just pushed up a replacement for the data path posted earlier today. The new zip file contains both a data path and a controller. As a reminder, I would prefer that you use your designs for Project 5 if you were successful, or nearly successful with Project 4. Please watch the blog for further updates.

Data path for Project 5

I have posted a data path model from Vijay to the Resources Page that you may use for Project 5 if you did not get Project 4 working. I would prefer that you use your own data path, but you may use this one if you would rather not spend more time debugging Project 4.

Project 5

I've finally posted a brief description of Project 5. It is as you expect - synthesize results from Project 4. You'll need to update your model to use the 2 port memory and then use the Xilinx tools to synthesize the entire model to the XUP board. The trick, as always, will be testing.

The TAs are working on a Project 4 model for you to use if you did not get Project 4 working completely. I will let you know when that becomes available.

I've not assigned a due date for this lab yet. We'll talk about that in class Thursday.

Data path diagram for Project 4

The TAs would like you all to submit a drawing of your data path for Project 4 when you turn in your simulation models. You should have this already as a result of your design work, so hopefully it will just be a matter of cleaning up and submitting a figure.

set is different

Although set is an R-Type instruction, it is a bit different than the others in that the register file should be disabled when executing set. The ALU control inputs don't matter, so you can use the same logic as for other R-Type instructions for that as well as the registers. However, you want to disable the register file so you don't accidentally store garbage when set terminates. Remember that it does not write to the register file, but instead uses the last 4 bits as a mask. Disabling the register file is the *only* difference and should be done by the controller.

Zero detection

One of the bits in your status register is set when both the outputs of the register file are zero. This is not hard to do - if any bit in either output is 1 then you know both outputs are not zero. However, there is not a component in the library to do this. You can construct one with a wad of OR gates, but that is painful. Thus, if you want to write a behavioral component that takes 2 word inputs and returns 1 if no bit in either word is 1, that's fine. It's a trivial component if you just use a loop to search each 16 bit word for a 1.

One two-port memory

If you are using the 2 port memory, you only need to instantiate 1 memory component in your data path. You then instantiate that component with the data signals and address signals for the instruction and data memories. If you go this route, you only need one initialization file and one dump file for the memory.

One potentially good reason to go this route is that the 2 port memory will synthesize when you get to that. The only downside is I think it introduces a bit more complexity in this project.

Do note that the format of the initialization file is different than the memory modules I wrote.
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