Project 1 thoughts

Some random thoughts on Project 1...

As many of you are realizing, just because a model simulates does not imply that it will synthesize.  Hardware synthesis is a different beast than program compilation.  The form of your model directly impacts the quality of the synthesis result.  Plus, you need more information to synthesize than to simulate.  Leave plenty of time for synthesis when you are doing your labs.

The hard problem from Project 1 is the grey code counter.  I talked to several folks about it in office hours and have a couple of thoughts to make the problem simpler.

1. Design separate circuits for counting up and counting down.  Feed the output of the state register into both circuits.  Then use a MUX and the count signals to select the "up" value or the "down" value.

2. Route enable and load directly to the appropriate signals on the register.  You don't need to include them in your truth table. If you do the design this way.

3. You'll need a number of MUXes to build the combinational circuits in your final design.  Build larger MUXes from smaller MUXes in their own model.  Then reuse that model throughout your design.



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