Project 5

I've finally posted a brief description of Project 5. It is as you expect - synthesize results from Project 4. You'll need to update your model to use the 2 port memory and then use the Xilinx tools to synthesize the entire model to the XUP board. The trick, as always, will be testing.

The TAs are working on a Project 4 model for you to use if you did not get Project 4 working completely. I will let you know when that becomes available.

I've not assigned a due date for this lab yet. We'll talk about that in class Thursday.