assert and report

As you are writing your VHDL models for the instruction interpreter, you may find that you want to print things out to the screen.  Viewing signals is great, but at times you may want to know if code is executing or grab the value of variable.  There are two commands that will help with this.

report "message"; - will print a message to the simulator output during execution.  This is handy to display information during execution.  The string value can be any string value, including strings containing simulation data.  Thus, you can print the value of variables during execution.

assert condition; - will abort execution if condition is false when it is executed.  By itself, this is not much fun to use.  However, the following is:

assert condition report message;

This command will not do anything if executed and condition is true.  However, if it is false it will terminate and report message to the output.  If you want to get fancy, you can also use a severity indicator:

assert condition report message severity severity_level;

where severity_level is either note, warning, error, or failure.  In most simulators, if you use note or warning, the assertion will not cause the simulator to abort and just produce the error.  Either error or failure will cause the simulation to abort.

For more info, look in the index of the Ashenden book under either report or assert.

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