The work package

Some of you have asked what work means in the notation:

work.mux41(beh)

All VHDL models must exist in a package.  Rather than force us to create new packages for every model, our tools provide a default package called work.  If you don't tell VHDL what package to put your designs in, they automatically go into the work package.  Thus, the above notation says to look in the work package for the beh architecture of the mux41 entity.

Project 1 thoughts

Some random thoughts on Project 1...

As many of you are realizing, just because a model simulates does not imply that it will synthesize.  Hardware synthesis is a different beast than program compilation.  The form of your model directly impacts the quality of the synthesis result.  Plus, you need more information to synthesize than to simulate.  Leave plenty of time for synthesis when you are doing your labs.

The hard problem from Project 1 is the grey code counter.  I talked to several folks about it in office hours and have a couple of thoughts to make the problem simpler.

1. Design separate circuits for counting up and counting down.  Feed the output of the state register into both circuits.  Then use a MUX and the count signals to select the "up" value or the "down" value.

2. Route enable and load directly to the appropriate signals on the register.  You don't need to include them in your truth table. If you do the design this way.

3. You'll need a number of MUXes to build the combinational circuits in your final design.  Build larger MUXes from smaller MUXes in their own model.  Then reuse that model throughout your design.



Project 2

Project 2 is up on the class website.  I realize everyone is in the midst of Project 1, but I pushed the project up for the TAs and thought I would make it available for everyone.  It is a simulation-only lab where you will develop an instruction interpreter.  Due date is not set.

Project 1 due dates

Project 1 will be due in your lab section starting Tuesday, February 10.  You must submit your lab report and demo your synthesis results in the laboratory section you are enrolled in unless you have permission from me not to.

I should be getting lab codes sometime next week, but the simulation tools are available on machines in the computing commons.  Thus, you can get your simulations running well before your lab section meets.

Room Change

As many of you are learning via the timetable or email, our class has been moved permanently to 1131 Learned.  The classroom we were in was too small to accommodate everyone who needed to enroll.  Thus, the folks in the EECS office jumped through a bunch of hoops to get the room officially changed.

Laboratory 1

The schedule for performing Project 1 is now on the Project 1 page. Basically, you'll go over it in lab starting January 27 and demonstrate it the following week. (Note that the Monday lab is a week behind, thus the Tuesday start date.)

Homework 1 due date

The due date for homework 1 is Tuesday, January 27 at the beginning of class. Sorry if there was some confusion about that.

Homework 1 file replaced

I've uploaded a PDF file for Homework 1 instead of the accidental LaTeX file.  You should be able to download and look at it now.

Laboratory 0

You'll find materials for your first laboratory on the projects page.  This is the only lab that requires no work outside lab hours.  You will run through the synthesis tool flow for a pre-defined example just to get familiar with the lab.

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