Project 3 due date

Project 3 due date is the week starting April 7. Note that the Monday lab is still a week behind.

Project 3 due date

Project 3 due date is the week starting April 7. Note that the Monday lab is still a week behind.

Project 3 due date

Project 3 due date is the week starting April 7. Note that the Monday lab is still a week behind.

Book references

There are references in the texts for topics I have been covering in class. However, it appears most of the information has been moved to the CD-ROM in the current edition of Computer Organization and Design.

In Ashenden, there are two examples of ALUs on p203 and 208. They are both more abstract that what I covered in class, but the structure of the code is identical. In Computer Organization and Design, ALU information is on the CD-ROM in chapter C.

In Computer Organization and Design, there is information on register files on the CD-ROM in chapter C.

In Computer Organization and Design, arithmetic is discussed starting on page 222.

Homework 3

Homework 3 is available on the homework page. Due date is March 12 in class.

Why sign extend works

By far the most common question that I'm getting in office hours is why sign extend works the way it does. I'll take a shot at explaining it here...

So, let's assume that I would like to add two binary numbers of different lengths. For example:

0101 + 01

It's a pretty simple matter to extend 11 with a pair of 0s to the left to make the numbers the same length. You do this all the time for decimal numbers:

0101 + 0001 = 0110

No problem. Let's to the same thing with subtraction and the same two values:

0101 - 01

add the zeros:

0101 - 0001

take the 2's compliment:

0101 + 1111



and all is well.

But what if we take the two's compliment before we extend 01 to 4 bits? In other words:

0101 + 11

If we add two zeros like we did earlier, we get the wrong answer:

0101 + 0011 = 1000

But, if we add two ones instead, we get the answer that we should:

0101 + 1111 = 0100

This is the situation we have with offset. The value is already in 2's compliment form before we extend it. Thus, we need to add 1's for negative numbers and 0's for positive numbers. As always, we can tell the difference between positive and negative because the high bit for a negative number is 1.

Never improvise...

This year is the first year I've used a sensitivity list with the instruction interpreter process model. Recall that we made our KURM CPU process sensitive to clk and reset. I completely forgot that you cannot use a wait in a process that has a sensitivity list. Our memory access must uses waits, so there's no way around this problem other than to eliminate the sensitivity list. Thankfully, this is quite simple.

Delete your sensitivity list for the process and add the following as the first line of your process:

wait on clk,reset;

This will accomplish the same thing - causing your process to wait on a change on either the clock or the reset.

assert and report

As you are writing your VHDL models for the instruction interpreter, you may find that you want to print things out to the screen.  Viewing signals is great, but at times you may want to know if code is executing or grab the value of variable.  There are two commands that will help with this.

report "message"; - will print a message to the simulator output during execution.  This is handy to display information during execution.  The string value can be any string value, including strings containing simulation data.  Thus, you can print the value of variables during execution.

assert condition; - will abort execution if condition is false when it is executed.  By itself, this is not much fun to use.  However, the following is:

assert condition report message;

This command will not do anything if executed and condition is true.  However, if it is false it will terminate and report message to the output.  If you want to get fancy, you can also use a severity indicator:

assert condition report message severity severity_level;

where severity_level is either note, warning, error, or failure.  In most simulators, if you use note or warning, the assertion will not cause the simulator to abort and just produce the error.  Either error or failure will cause the simulation to abort.

For more info, look in the index of the Ashenden book under either report or assert.

Conditional insructions

Some of you have been asking the TAs what to do with the remaining 7 op codes give that we only have 9 instructions and 4 bits to describe them.  We have 7 conditional instructions that we've not discussed yet.  Basically, they are identical to unconditional instructions, but will execute only when the status nybble is not zero.  See the bottom of page 3 of the ISA for more information, but modeling them simply requires: (i) an IF statement around your unconditional definition; or (ii) copying the unconditional operation and making the copy conditional.

I plan to talk about this in class tomorrow, but some of you beat me to it and started asking questions.

Project 2 due date

Project 2 will be due in lab starting March 3.