Zero detection

One of the bits in your status register is set when both the outputs of the register file are zero. This is not hard to do - if any bit in either output is 1 then you know both outputs are not zero. However, there is not a component in the library to do this. You can construct one with a wad of OR gates, but that is painful. Thus, if you want to write a behavioral component that takes 2 word inputs and returns 1 if no bit in either word is 1, that's fine. It's a trivial component if you just use a loop to search each 16 bit word for a 1.

One two-port memory

If you are using the 2 port memory, you only need to instantiate 1 memory component in your data path. You then instantiate that component with the data signals and address signals for the instruction and data memories. If you go this route, you only need one initialization file and one dump file for the memory.

One potentially good reason to go this route is that the 2 port memory will synthesize when you get to that. The only downside is I think it introduces a bit more complexity in this project.

Do note that the format of the initialization file is different than the memory modules I wrote.

Project 4 library pushed up

The library for Project 4 is now available on the Resources Page. This is the same library that you used for Project 3 with an example ALU and register file in case you did not get your behavioral models working for Project 3. You can just as easily use your models as the models provided in the library.

Project 4 due date

As I outlined in class, Project 4 will be due starting April 21. Remember that it is a simulation only lab.

Simplification for Projects 4 and 5

I've decided to make a couple of simplifications of KURM09 for Projects 4 and 5.

First, you do not need to implement conditional instructions. Recall that conditional instructions (addc, subc, etc) only execute if the status register is non-zero and are no-ops otherwise. Thus, the only instruction that will look at the status register is bra and we covered that instruction in class. I don't think we've discussed them sufficiently in class for me to ask you to implement them and it should simplify the last two labs a bit.

Second, the status register will be updated after every instruction. This simply means that the status register is clocked and will never be disabled. Note that bra does not access the register file in any defined way. Thus, the contents of the status register can be any value after bra executes. In effect, status register values for the next state after bra are don't cares.

Hopefully these changes will simplify things by making the enable logic for the register file and the status register simpler. The status register is no longer involved in determining when the register file should be enabled and the status register is now always enabled.

Project 4 available

Project 4 is now available from the Laboratory Page. The objective of the lab is to design a data path exactly like the one we've been talking about in class.

To things to note. First, it is a simulation only lab - no synthesis this time around. Second, the library for designing your data path will be available after completing Project 3. The only difference between the Project 4 and Project 3 libraries is the inclusion of ALU and register file models. If you want to use your own models for those components, feel free to do so.

Homework Solutions

To help you prepare for the exam, the TAs have provided solutions for homework 1-3. They can be found on the Resources Page.

Following along in the text

If you're interesting in following what we're doing in class in the text, we're starting Chapter 4 of Computer Organization and Design.  In particular, Section 4.3 covers the design of a datapath.  The book uses a different processor than we do that is somewhat more complicated, but its structure is identical to KURM09.

Midterm Exam

The midterm is scheduled for April 2 in class.  A set of study topics is available on the exams page.  Bring questions to class Thursday and Tuesday.

Combinational not Sequential ALU

The project 3 description specifies a sequential ALU. It should be combinational. Also, the VHDL skeleton uses a control input with 3 values (2 downto 0). Only two are required. I have posted an updated project description should you want to download a new version. However, these are the only changes.