Project 5

I've finally posted a brief description of Project 5. It is as you expect - synthesize results from Project 4. You'll need to update your model to use the 2 port memory and then use the Xilinx tools to synthesize the entire model to the XUP board. The trick, as always, will be testing.

The TAs are working on a Project 4 model for you to use if you did not get Project 4 working completely. I will let you know when that becomes available.

I've not assigned a due date for this lab yet. We'll talk about that in class Thursday.

Data path diagram for Project 4

The TAs would like you all to submit a drawing of your data path for Project 4 when you turn in your simulation models. You should have this already as a result of your design work, so hopefully it will just be a matter of cleaning up and submitting a figure.

set is different

Although set is an R-Type instruction, it is a bit different than the others in that the register file should be disabled when executing set. The ALU control inputs don't matter, so you can use the same logic as for other R-Type instructions for that as well as the registers. However, you want to disable the register file so you don't accidentally store garbage when set terminates. Remember that it does not write to the register file, but instead uses the last 4 bits as a mask. Disabling the register file is the *only* difference and should be done by the controller.

Zero detection

One of the bits in your status register is set when both the outputs of the register file are zero. This is not hard to do - if any bit in either output is 1 then you know both outputs are not zero. However, there is not a component in the library to do this. You can construct one with a wad of OR gates, but that is painful. Thus, if you want to write a behavioral component that takes 2 word inputs and returns 1 if no bit in either word is 1, that's fine. It's a trivial component if you just use a loop to search each 16 bit word for a 1.

One two-port memory

If you are using the 2 port memory, you only need to instantiate 1 memory component in your data path. You then instantiate that component with the data signals and address signals for the instruction and data memories. If you go this route, you only need one initialization file and one dump file for the memory.

One potentially good reason to go this route is that the 2 port memory will synthesize when you get to that. The only downside is I think it introduces a bit more complexity in this project.

Do note that the format of the initialization file is different than the memory modules I wrote.

Project 4 library pushed up

The library for Project 4 is now available on the Resources Page. This is the same library that you used for Project 3 with an example ALU and register file in case you did not get your behavioral models working for Project 3. You can just as easily use your models as the models provided in the library.

Project 4 due date

As I outlined in class, Project 4 will be due starting April 21. Remember that it is a simulation only lab.

Simplification for Projects 4 and 5

I've decided to make a couple of simplifications of KURM09 for Projects 4 and 5.

First, you do not need to implement conditional instructions. Recall that conditional instructions (addc, subc, etc) only execute if the status register is non-zero and are no-ops otherwise. Thus, the only instruction that will look at the status register is bra and we covered that instruction in class. I don't think we've discussed them sufficiently in class for me to ask you to implement them and it should simplify the last two labs a bit.

Second, the status register will be updated after every instruction. This simply means that the status register is clocked and will never be disabled. Note that bra does not access the register file in any defined way. Thus, the contents of the status register can be any value after bra executes. In effect, status register values for the next state after bra are don't cares.

Hopefully these changes will simplify things by making the enable logic for the register file and the status register simpler. The status register is no longer involved in determining when the register file should be enabled and the status register is now always enabled.

Project 4 available

Project 4 is now available from the Laboratory Page. The objective of the lab is to design a data path exactly like the one we've been talking about in class.

To things to note. First, it is a simulation only lab - no synthesis this time around. Second, the library for designing your data path will be available after completing Project 3. The only difference between the Project 4 and Project 3 libraries is the inclusion of ALU and register file models. If you want to use your own models for those components, feel free to do so.

Homework Solutions

To help you prepare for the exam, the TAs have provided solutions for homework 1-3. They can be found on the Resources Page.
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