Midterm Exam
Date: Thursday, April 2

RTL Design
  • Word gates (AND, OR, etc)
  • Registers
  • MUX and DEMUX
  • Adders and subtractors
  • Multipliers
  • Cascading (Building larger devices from smaller devices)
  • Sequential system design
  • Combinational ALU design
  • Sequential ALU design
Register Files
  • Selecting output values
  • Storing input values

There will be no VHDL on this exam

Final Exam
Date: 7:30-10:00 AM, Tuesday May 12 (NOT my choice!)

All Midterm Topics - See above

Data path design
  • Mathematical instructions implementation (R-Type)
  • Memory access (M-Type)
  • Branches and Jumps (B-Type and J-Type)
  • Pipelining
Controller design
  • Single state controllers
  • Multi-state controllers
  • Pipeline controllers
Hazard detection and avoidance
  • Read after Write hazards
  • Forwarding units
  • Branch hazards
  • Principle of Locality
  • Calculating cache hits
  • Translating addresses to cache indexes and tags

There will be no VHDL on this exam. Virtually all of these topics are discussed in Chapter 4 of your text. Chapter 3 discusses issues related to arithmetic functions. Chapter 5 discusses caching.