The objective of this project is to develop and simulate models for basic behavioral VHDL components and use those components to define a structural model. You will design, simulate and implement a number of RTL components and use them to construct a simple counter. You will write VHDL and simulate all of the laboratory problems, but will only synthesize those required to build the counter.

Links below provide you with the lab assignment, instructions for setting up the tools and getting started, a template for your lab report, and a copy of the TA's notes for the lab lecture. The two system files are support files you may find useful.

Download Lab Assignment
Download Lab Instructions
Download Lab Write-up Template
Download Lab Lecture Notes
Download Lab Lecture Slides
Download system.vhd
Download system.ucf

You will go over this project during lab starting Tuesday, January 27. (The Monday lab is a week behind.) You will build your models, demonstrate them and submit them to the TAs starting Tuesday, February 10. (Note the extension from February 3.)