The objective of this project is to implement an instruction interpreter for the KURM07 (KU RISC Machine 2007) CPU that will serve as your semester project. This device is a simple 16-instruction RISC-style CPU. As is traditional in a RISC architecture, a small number of highly efficient instructions and addressing modes will be defined.

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This is a simulation only lab. Send your VHDL source files and test programs to the TAs via email. Due date is the week of March 3.