The objective of the laboratory is to synthesize your multi-stage processor designed for Project 4. To do this, you must modify your processor to use the 2 port memory provided in the memory models library. When you use this model in synthesis mode, the Xilinx tools will map the memory to a block RAM available on the XUP board. Although you can use a UCF file to choose a particular block RAM for system memory, it is simpler not to as the Xilinx tools will automatically select a block RAM for you.

To test your model, simply load programs into memory using the memory initialization file, reset the processor and watch it execute them. You should be able to use the same programs used for earlier projects. However, if you used the single port memory model you will need to convert your hex representations to binary representations. This is quite simple to do and can be automated with a script written in virtually any scripting language.

Libraries as well as a sample data path for the assignment can be found on the Resources Page.

Due: TBD - we will talk about this in class.

There is no formal write-up for this project.