The objective of the Digital Systems Design laboratory is to design, simulate and implement a RISC microprocessor. The laboratory begins with an introduction to defining and simulating simple RTL components in VHDL and ends with synthesis of a pipelined microprocessor to a Xilinx FPGA. You will learn VHDL, the ModelSim VHDL simulation environment, Xilinx FPGA synthesis tools, and FPGA debugging tools. The laboratory period for this course provides a time for you to access equipment and software for performing your lab experiments. Attendance is not compulsory, but the TAs will lecture on use of VHDL simulators, VHDL synthesis tools and FPGA synthesis. You are responsible for learning this material on your own if you do not attend. The TAs will also be available for project demonstrations and assistance debugging during lab period.

Lab assignments will involve using a VHDL simulation and synthesis environment. The official simulation environment used for this class is a part of the ModelSim tool suite available on the EECS computing systems. The department has unlimited ModelSim licenses, but we cannot license individual student computers. Thus, you must use the EECS systems in Eaton Hall to use the tools we use in lab. Please allow plenty of computer access time to complete your projects. Several free simulators are available for Windows and Linux. Should you choose to use one of these simulators, please keep in mind that your projects will be graded using the ModelSim environment.

The official synthesis target for your designs is the Xilinx prototyping board available in the laboratory. VHDL synthesis tools are available to automatically synthesize FPGA implementations from VHDL. However, do not assume that simply because your solutions simulate they will synthesize successfully. ChipScope is available to assist you in debugging your implementations. Although you may purchase your own prototyping boards, the department boards are only available in the EECS 443 laboratory and must remain there.

The instruction set architecture (ISA) for the KURM08 that we will be designing is available here. References in all lab assignments to the CPU specification refer to this document.