Syllabus as distributed on the first day of class
Instruction Set Architecture for the KURM08 CPU we will be desiging this semester.
A brief introduction to VHDL written by Peter Ashenden. Pay attention to the VHDL'93 features.
An emacs mode for writing VHDL with exellent electric mode and templates for various constructs. Lots of really cool templates and VHDL creation utilities. An excellent resource for writing VHDL in emacs.
VHDL memory model used to test our CPU design. Read the internal documentation!
VHDL memory model that will synthesize to RAM on the XUP board. Use this module when you start synthesizing systems that require memory access.
A free download from Xilinx with a VHDL simulator and synthesis tools. Available for Windows and Linux. These tools should be limited versions of the tools we have in lab. Thus, you can work on your designs outside of lab period.
Sample RTL library for defining the KURM CPU. Most models in this library are synthesizable.
A library of components for use in Lab 4 including a register file and ALU model.
Solution for Homework 1
Solution for Homework 2
Solution for Homework 3
A multistate solution for Project 4 that may be used as a starting point for Project 5.