Introduction to Digital Logic Design

Prof. James P.G. Sterbenz <jpgs@eecs.ku.edu>
Department of Electrical Engineering and Computer Science,
The University of Kansas

Latest News

Final exam: 18 May 10:30–13:00 in Learned 2112

Optional review session: 15 May 10:30–13:00 in Learned 2112

Course Description

EECS 140
EECS 141 honors section
4 credit hours

An introductory course in digital logic circuits covering number representation, digital codes, Boolean Algebra, combinatorial logic design, sequential logic design, and programmable logic devices.

Corequisites

MATH 121 (Calculus I)

Time and Location

Lecture: 11:00–12:15 Tue. Thu.
Learned 2112, Lawrence Campus
Laboratories: bginning the week of 29 Jan. (see table for times)
Eaton 2010

Type Section ID Time Day Room Instructor
lecture  140-1000   61379   11:00–12:15   Tue.Thu.   Learned 2112  Sterbenz
honors lecture 141-1000 62449 11:00–12:15 Tue.Thu. Learned 2112 Sterbenz
lab140-1100 65781 11:00–12:50 Mon. Eaton 2010 Parr
honors lab141-1200 65787 15:00–16:50 Mon. Eaton 2010 Baijot
lab140-1300 62625 12:30–14:20 Tue. Eaton 2010 Parr
lab140-1400 62623 13:00–14:50 Mon. Eaton 2010 Baijot
lab140-1500 61380 14:30–16:20 Tue. Eaton 2010 Ortiz
lab140-1600 61382 14:30–16:20 Thu. Eaton 2010 Ortiz

Instructor Office hours

Tue. Thu. 09:00–10:30 in 3036 Eaton
+1 785 864 8846
or by appointment
+1 785 864 7890

I will generally not be in my Eaton office at other times, so you are strongly encouraged to email or call one of my office numbers in advance if you need to see me outside of normal office hours. While you can probably find my mobile, home, and skype numbers without much difficulty, I expect these to only be used for emergency situations.

All email correspondence to me regarding this class must be addressed To: James P.G. Sterbenz <jpgs@eecs.ku.edu> with a Subject: beginning EECS140 -. Nonconforing email is likely to be misfiltered and not be read.

Graduate Teaching Assistants and Office Hours

Fabrice Baijot<bricefab@ittc.ku.edu> Mon. 11:00–13:00
Jorge Ortiz <ortizj@ittc.ku.edu> Tue.
Thu.
12:30–14:30
Zachary Parr <zparr@ittc.ku.edu> Mon.
Wed.
10:00–11:00
10:00–13:00
in 2013 Eaton

Course Information

Schedule and Topics

This table will be filled in as the semester progresses. All dates and the exam sequence are tentative and subject to change, with the exception of spring break and the final exam dates set by KU.

EECS 140 and 141 Spring 2007 Tentative Schedule
Date Lecture Reading Homework
Subject Key Concepts Required Optional # Assignment Due
23 Jan. Administrivia and Ethics
25 Jan.–8 Feb.  Introduction and Methodology     DLD:1  H:1  1  find and read TI Datasheets for
7404, 7408, 7432, and 74158
print 7404 and bring to class
30 Jan.
 2   DLD:1.2–1.6 6 Feb.
 3   DLD:1.7–1.9 13 Feb.
13 Feb.–1 Mar. Combinational Basics logic functions
truth tables
gates
boolean algebra
Karnaugh maps
binary codes
encoders / decoders
VHDL
 DLD:2  H:2–3  4   DLD:2.1–2.11, 2.14–2.15 20 Feb.
 5   DLD:2.16–2.20, 2.23
 Suplement:2S.1–2S.2
27 Feb.
 6   DLD:2.24–2.31, 2.33 6 Mar.
13 Mar. Exam 1
20, 22 Mar. Spring Break
6 Mar.–17 Apr. Numeric Basics number representation
unsigned integers
binary, ocatal, hexadecimal
adders and subtractors
comparators
multipliers
 signed and complement integers 
signed arithmetic
 fixed and floating point numbers 
 DLD:3  H:4
 VHDL:1–4
 7   DLD:3.1–3.4, 3.6–3.7,
     3.10–3.14, 3.16–3.19
3 Apr.
 8   DLD:3.22–3.23, 3.26,
     3.29, 3.31–3.33, 3.35
10 Apr.
 9   DLD:3.37–3.39, 3.44
     3.47–3.48, 3.51, 3.56,
     3.58, 3.63–3.64
17 Apr.
17 Apr.–3 May   Sequential Basics  latches and flip flops
registers
shift registers
counters
finite state machines
synchronous circuits
 DLD:4  H:6–8  10   DLD:4.1–4.2, 4.4, 4.8,
     4.10–4.11, 4.13, 4.16
1 May 
 11   DLD:4.17–4.20
     4.22–4.24
8 May 
8 – 10 May  Memories RAMs and ROMs
multiport memories
error detection and correction
10 May  Last Class
18 May  Final Exam
10:30–13:00 Fri.
28 May  Final Grades Available

Entries in the Reading column are chapters and sections.
Entries in the Homework column are problems at the end of the chapter.

DLD = Ashenden Digital Logic Design
VHDL = Ashenden Student's Guide to VHDL
DB = TI Digital Logic Pocket Data Book
H = Hwang Digital Logic and Microprocessor Design
Supplement = supplementary exercises not in Ashenden; follow hyperlink


Books and Materials

Required Textbooks (EECS 140 and 141)

These textbooks and the corresponding required readings in the table are essential for success in this course. Students are responsible for knowing all of this material regardless of whether or not explicitly covered in lectures.

Peter J. Ashenden,
Digital Logic Design: An Embedded Systems Approach using VHDL/Verilog,
Morgan Kaufmann, 2008
A preprint of part of the first part of this book will be available for purchase at the KU Bookstore, Kansas Union approximately a week before the first class. The second part will be available mid-semester.

Digital Logic Pocket Data Book,
Texas Instruments, SCYD013A, 2004

Optional Textbook (required for EECS 141)

Peter J. Ashenden,
The Student's Guide to VHDL,
Morgan Kaufmann, 1998

Introduction to VHDL used in subsequent computer architecture courses, in particular EECS 443.

Supplementary Textbooks

These books are on reserve in the Spahr Engineering Library

Enoch O. Hwang,
Digital Logic and Microprocessor Design with VHDL,
Thomson, 2006

This book has been used recently in EECS 140 and is a good supplementary reference for students that want a different perspective on the material.

Peter J. Ashenden,
The Designer's Guide to VHDL, 2nd edition,
Morgan Kaufmann, 2002

Comprehensive coverage of VHDL; more advanced than The Student's Guide.

Required Materials

Half-size logic design template (ANSI Y32.14, IEEE 91a, or MIL-STD-806C compliant).
The KU bookstore has some Pickett 1222i in the supply section and has more on order (they are brown). I do not recommend the thick Berol (green) templates currently in the bookstore since they are harder to use with conventional pencils.

All logic diagrams drawn for homework and exams must be done with the aid of a logic design template and straight edge. Hand-sketched gates and blocks are not acceptable. Homework and lab assignments are expected to be neatly prepared. Assignments, labs, and exam questions not meeting these requirements will receive a grade of zero on the corresponding sections.


Grading

This course will be graded using a the ranges in the following Grade Scale Table. It is possible that the grade distribution will be such that the numerical values will shift slightly downward, i.e. a score in the left column will result in a grade of at least the letter in the right column.

The relative contribution of course assignments to the overall grade is given in the Grade Weight table.

Grade Scale
Average Grade
  90–100% A
80–89% B
70–79% C
60–69% D
00–59% F
     
Grade Weight
Exam 1 15%
Exam 2 15%
Final Exam 25%
Labs 25%
Homework
Quizzes
20%

Exams and Quizzes

All exams and quizzes will be closed book and closed notes. The use of all electronic devices is prohibited during exam periods. You must read the undergraduate course exam information and the exam section of the academic integrity Web pages.

EECS 140 Spring 2007 Exam Results
Exam Minimum Mean Std. Dev. Median Maximum
Midterm 1 37.0  81.1 13.7 84.0 100.0 
Midterm 2 36.0  82.3 13.6 87.0 98.0 
Final

Short pop quizzes may be occasionally given if deemed necessary. Example motivations include a pop quiz at the beginning of the class to encourage prompt arrival, or to guage student understanding of the material in between exams.

Homework and Laboratory Assignments

All homework and laboratory assignments must be individually prepared. You must read the undergraduate homework submission guidelines and the homework section of the academic integrity Web pages.


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