Introduction to Digital Logic Design

Prof. James P.G. Sterbenz <jpgs@eecs.ku.edu>
Department of Electrical Engineering and Computer Science,
The University of Kansas

Latest News

Final exams are generally given in the same room as the lecture, and this is the case with 140.

Course Description

EECS 140
EECS 141 honors section: If you are a strong student, you may wish to consider taking the honors section of this course. At the cost of some extra reading, homework, and alternate lab exercises, you will get the benefit of this appearing on your transcript and resume.
4 credit hours

An introductory course in digital logic circuits covering number representation, digital codes, Boolean Algebra, combinatorial logic design, sequential logic design, and programmable logic devices.

Corequisites

EECS 140: MATH 104 (Precalculus)
EECS 141: MATH 121 (Calculus I) and acceptance in KU Honors Program or permission of instructor

Fall 2008 Offering Details

Note: this page contains information specific only to the section taught by James P.G. Sterbenz. Further information common to both sections including homework assignments is located on the EECS 140 wiki.

Time and Location

Lecture: 11:00–12:15 Tue. Thu.
Learned 1131, Lawrence Campus
Laboratories: beginning 28 August (see table for times)
Eaton 2010

Type Section ID Time Day Room Instructor
lecture  140-1100  15894   11:00–12:15   Tue.Thu.   Learned 1131  Sterbenz
 honors lecture  141-105044978 11:00–12:15 Tue.Thu. Learned 1131 Sterbenz
lab 140-xxxx
141-xxxx
43128
34106
15:00–16:50 Mon. Eaton 2010 Ortiz
lab 140-xxxx
141-xxxx
30628
43148
09:00–10:50 Tue. Eaton 2010 Torres
lab 140-xxxx
141-xxxx
30632
43160
14:30–16:20 Tue. Eaton 2010  Varatharajan 
lab 140-xxxx
141-xxxx
30634
43189
15:00–16:50 Wed. Eaton 2010 Ortiz
lab 140-xxxx
141-xxxx
34848
43152
09:00–10:50 Thu. Eaton 2010 Torres
lab 140-xxxx
141-xxxx
30630
43155
13:00–14:50 Thu. Eaton 2010 Varatharajan
supplemental 16:00–18:00 Mon. Eaton 1005A Valdivia
supplemental 16:00–18:00 Tue. Learned 3153 Coble

Instructor Office hours

Thu. 12:30–14:30 in 3036 Eaton
+1 785 864 8846
or by appointment
+1 785 864 7890

I will generally not be in my Eaton office at other times, so you are strongly encouraged to email or call one of my office numbers in advance if you need to see me outside of normal office hours. While you can probably find my mobile, home, and skype numbers without much difficulty, I expect these to only be used for emergency situations.

All email correspondence to me regarding this class must be addressed To: James P.G. Sterbenz <jpgs@eecs.ku.edu> with a Subject: beginning EECS140 -. Nonconforming email is likely to be misfiltered and not be read.

Graduate Teaching Assistants and Office Hours

Jorge Ortiz <ortizj@ittc.ku.edu> Thu.
Fri.
15:00–16:00
13:00–14:00
Sarvesh Varatharajan <sarvesh@ittc.ku.edu> Fri. 11:00–13:00
German Torres <germantf@ku.edu> Mon. 12:00–14:00
in 3029 Eaton

Undergraduate Supplemental Instructors and Office Hours

Jacob Coble <jcoble@eecs.ku.edu> Tue. 16:00–17:00
Andrea Valdivia <avaldivia58@hotmail.com> Wed. 10:00–11:00
in 3029 Eaton

Course Information

Schedule and Topics

This table will be filled in as the semester progresses. Note that additional information about each homework assignment is located on the 140 wiki, as linked by each assignment number in the table.

EECS 140 and 141 Fall 2008 Tentative Schedule
Date Lecture Reading Homework
Subject Key Concepts Required
 140 & 141 
 Optional 140 
 Required 141 
  #   Problems Due
 21 – 
 26 Aug. 
Administrivia
and Ethics
26 Aug.  Design Concepts design process
 binary numbers 
conversion
 BV: 1 01 handout  02 Sep. 
28 Aug.  Introduction to
Logic Circuits
variables & logic functions
switches
inversion
truth tables
logic gates & networks
 BV: 2.1–2.4 
 DB: 08, 11, 32, 04 
02  2.2, 2.5, 2.8, 
 2.13, 2.14, 2.18, 
 2.19, 2.21, 2.31, 
 2.35 
 09 Sep. 
02 Sep.  Boolean algebra
Venn diagrams
 BV:2.5
04 Sep.  synthesis
SOP, minterms
POS, maxterms
 BV:2.6
11 Sep.  NAND and NOR gates  BV: 2.7 
 DB: 00, 02, 20, 51 
03  2.37, 2.38, 2.39, 
 2.45, 2.47 
 Quartus II 
 16 Sep. 
09 Sep.  multiplexors  BV: 2.8 
16 Sep.  CAD tools  BV: 2.9  04  2.50, 2.51, 2.52   23 Sep. 
18 Sep.  VHDL intro.  BV: 2.10–2.11 
23 Sep.  Implementation
Technology
transistor switches
NMOS gates
CMOS gates
 BV: 3.1–3.3  05  3.1, 3.2, 3.4, 
 3.5, 3.6, 3.7 
 30 Sep. 
25 Sep.  negative logic
standard chips
 BV: 3.3–3.5 
30 Sep.  programmable logic
PLAs and PALs
CPLDs
 BV: 3.6–3.6.4  06  3.9, 3.10, 3.13, 
 3.36, 3.38, 3.42 
 use Fig. 3.27 
 instead of 3.66 
 07 Oct. 
02 Oct.  programmable logic
FPGAs
standard cells
gate arrays
 BV: 3.6.5–3.7 
07 Oct.  propagation delay
power dissipation
fan-in and fan-out
buffers
 BV: 3.8.5–3.8.8 
 DB: 34 
 BV: 3.8.1–3.8.4 07  3.44, 3.46, 3.48, 
 3.49, 3.50, 
 3.51 (do timing simulation) 
 – 
 EECS141 only: 
 3.36, 3.48, 3.42 
 using Fig. 3.66 and 3.65 
 14 Oct. 
09 Oct.  tri-state buffers
transmission gates
XOR gates
 BV: 3.8.8–3.9, 3.11 
 DB: 125, 126, 86 
 BV:3.10
14 Oct.  Optimized
Implementation
of
Logic Functions
Karnaugh maps:
SOP
prime implicants
cover, cost
 BV: 4.1–4.2
16 Oct.  fall break: no class
21 Oct.  Karnaugh maps:
strategy
POS, don't care
multiple outputs
Exam 1 review
 BV: 4.2–4.5 08  4.1, 4.3, 4.4, 4.6, 4.10  28 Oct. 
23 Oct.  Exam 1: Chapters 1–3
28 Oct.  multilevel synthesis  BV: 4.6–4.7 09  4.16, 4.17, 4.18, 4.19,
 4.27
 (K-map
  instead of Sec. 4.10)
 04 Nov. 
30 Oct.  cubical representation  BV: 4.8, 4.12–4.13
04 Nov.  Number
Representation
and
Arithmetic Circuits
binary representation:
unsigned integers
half adders
full adders: ripple carry
 BV: 5.1–5.2     10  5.1, 5.4, 5.5,
 5.6, 5.7
 – 
 EECS141 only: 5.8
 11 Nov. 
06 Nov.  binary representation:
signed-magnitude
one's complement
two's complement
addition and subtraction
 BV: 5.3   
11 Nov.  fast adders
comparators
VHDL design
 BV: 5.4–5.5 
 DB: 182, 283, 85, 181 
 BV: 5.6 11  5.13, 5.14,
 5.25, 5.26, 5.27
 – 
 EECS141 only:
 5.15, 5.28
 18 Nov. 
13 Nov.  binary representation:
floating point
BCD
ASCII
 BV: 5.7–5.9 
18 Nov.   Combinational-Circuit 
Building Blocks
multiplexors  BV: 6.1
 DB: 157, 153
12  6.1, 6.4, 6.13
 6.23, 6.24, 6.30
 6.35 (use Fig. 6.52)
 – 
 EECS141 only:
 6.7, 6.9, 6.26
 03 Dec. 
12:00  
noon  
20 Nov.  decoders and encoders
demultiplexors
code converters
comparators
Exam 2 review
 BV: 6.2–6.7
 DB: 139, 138, 154, 
         148, 247, 85 
25 Nov.  Exam 2: Chapters 4–5,
 tri-state and transmission gates, multiplexors from Chapter 3 
27 Nov.  Thanksgiving break: no class
02 Dec.  Flip-Flops,
Registers, Counters,
and a
Simple Processor
latches
gated SR and D latches
setup and hold time
flip-flops:
master-slave
edge-triggered
 BV: 7.1–7.4
 DB: 279, 74, 73 
13  7.1, 7.3, 7.5, 7.8
 7.13, 7.17, 7.21
 – 
 EECS141 only:
 7.22 (instead of 7.21),
 7.33
 12 Dec. 
12:00  
noon  
04 Dec.  flip-flops:
preset and clear
JK and T
registers
shift registers
counters:
asynchronous
synchronous
 BV: 7.5–7.13, 7.16 
 DB: 164, 166, 93, 90 
 BV: 7.14–7.15
09 Dec.  Synchronous
Sequential Circuits
state machines:
diagrams and tables
state assignment
 BV:8.1–8.2 14  8.1, 8.2
 8.5, 8.6 (don't minimize)
 – 
 EECS141 only:
 minimize 8.5, 8.6
 optional: 
 check 
 answers 
 in back 
 of text
11 Dec.  Mealy machines
adder example
 BV:8.3–8.5  BV:8.6–8.12
16 Dec.  Optional final exam review:
16:00 – 17:00 in Learned 3153
17 Dec. 
Wed. 
Final Exam: Chapters 6–8 and comprehensive
10:30–13:00
30 Dec.  Final Grades Available

Entries in the Reading column are chapters and sections.

BV = Brown and Vranesic, Fundamentals of Digital Logic with VHDL Design
VHDL = Ashenden, Student's Guide to VHDL
DB = TI, Digital Logic Pocket Data Book (numbers refer to the circuit numbers at the top of the pages)


Exams

Midterm Exam 1

Midterm Exam 2

Final Exam 3

Note: while the final exam will concentrate on Chap 6–8, there will be questions that cover Chap. 1–5; therefore students are strongly recommended to review all course material and study guides.

Exam Results

See the main course page for futher details on grading.

EECS 140/141 Fall 2008 Exam Results
Exam Statistics Distribution
 Min   Med   Max   Mean   Std Dev   0–49   50–54   55–59   60–64   65–69   70–74   75–79   80–84   85–89   90–94   95–100 
 Midterm 1  30  77  98  72  17 
 Midterm 2  32  76  99  76  16  10 
 Final  37  76  92  72  12  10 

Navigation: Up: coursesTop: James P.G. Sterbenz


Last updated 03 February 2009 – Valid XHTML 1.1Lynx inspectedW3C AAA Conformance
©2006–2009 James P.G. Sterbenz <jpgs@eecs.ku.edu>