Introduction to Digital Logic Design

Prof. James P.G. Sterbenz <jpgs@eecs.ku.edu>
Department of Electrical Engineering and Computer Science,
The University of Kansas

Latest News

Final exam review scheduled for 14:00–15:00 in Eaton 2010. The weekly help seesion will then be held immediately after. This will be a rather quick walk-through of all four study guides linked in the Exam section below. I will not hand these out again, so you may wish to bring your own copies. If you have significant problems with specific material in this course you should stay for the help session, or go to office hours of the instructor, GTAs, or supplemental instructors.

Homework 11 can be picked up from the EECS office Mon. afternoon or Tue. morning before the exam

Schedule table now accurate through the end of the semester.

Logic summary foils may be updated to include flip-flops this weekend.

EECS Honors Research Tour of ITTC will be held next semester. All current EECS 141 (and 169) students will be invited. The EECS Honors Mixer will be held every semester in Nunemaker Hall.

Exams are closed book, closed notes, no calculator. The only thing you may use is your writing implement and logic design template. All logic gates on the exam must be drawn using your template, and your logic template must not have any writing on it to use in the exam.

New homework correction procedure: If you have any question or concern about the way a problem has been graded you are welcome to show me after class, but must attach a short note to the homework and resubmit to me the following class. I will look at it and submit to the GTA who initially graded, who will recondsider (consulting with me if necessary). If you are not satisfied with their explanation (which may or may not change your grade), show me and we'll work through the problem together.

Please email me immediately if you go to any scheduled office hours or help session and nobody is there.

If you are enrolled in EECS 140 or 141, free to join the Facebook group.

Course Description

EECS 140
EECS 141 honors section
4 credit hours

An introductory course in digital logic circuits covering number representation, digital codes, Boolean Algebra, combinatorial logic design, sequential logic design, and programmable logic devices.

EECS 141 is open to students in the KU honors program or by permission of the instructor. Cost: some additional reading, homework, and a more challenging laboratory exercise. Benefit: honors course on your transcript and resume, higher visibility to your instructor, special events. If you are a strong student, you may wish to consider taking the honors section of this course.

Corequisites

EECS 140: MATH 104 (Precalculus)
EECS 141: MATH 121 (Calculus I) and acceptance in KU Honors Program or permission of instructor

Fall 2010 Offering Details

Note: this page contains information specific only to the section taught by James P.G. Sterbenz. Further information common to both sections including homework assignments is located on the EECS 140 wiki.

Time and Location

Lecture: 11:00–12:15 Tue. Thu.
Malott 2001, Lawrence Campus
Laboratories: beginning 28 August (see table for times)
Eaton 2010

Type Section ID Time Day Room Instructor
lecture  140-1100  15003   11:00–12:15   Tue.Thu.   Malott 2001  Sterbenz
 honors lecture  141-105036309 11:00–12:15 Tue.Thu. Malott 2001 Sterbenz
lab 140-1600
141-1500
34469
28617
15:00–16:50 Mon. Eaton 2010 Fokum
lab 140-1200
141-1100
26261
34489
09:00–10:50 Tue. Eaton 2010 Nguyen
lab 140-1500
141-1400
26265
34509
14:30–16:20 Tue. Eaton 2010 Fokum
lab 140-1700
141-1600
26267
34535
15:00–16:50 Wed. Eaton 2010 Nguyen
lab 140-1300
141-1200
29185
34495
09:00–10:50 Thu. Eaton 2010 Zhang
lab 140-1400
141-1300
26263
34501
13:00–14:50 Thu. Eaton 2010  Zhang 
supplemental 14:00–15:00 Mon. Learned 1136 Rodriguez
supplemental 13:00–14:00 Tue.  Learned 3150  Fuller

Instructor Office hours

Tue., Thu. 12:30–13:30 in 3036 Eaton
+1 785 864 8846
or by appointment
+1 785 864 7890

I will generally not be in my Eaton office at other times, so you are strongly encouraged to email or call one of my office numbers in advance if you need to see me outside of normal office hours. While you can probably find my mobile, home, and skype numbers without much difficulty, I expect these to only be used for emergency situations.

All email correspondence to me regarding this class must be addressed To: James P.G. Sterbenz <jpgs@eecs.ku.edu> with a Subject: beginning EECS140 - or To: James P.G. Sterbenz <jpgs@eecs.ku.edu> with a Subject: beginning EECS141 -. Nonconforming email is likely to be misfiltered and not be read.

Graduate Teaching Assistants and Office Hours

Daniel T. Fokum <fokumdt@ku.edu> Mon.
Tue.
Wed.
13:00–14:00
11:00–12:00
10:00–11:00
Anh Nguyen <anguyen@ku.edu> Tue.
Wed.
14:00–16:00
11:00–12:00
Yuanyuan Zhang <yyzhang@ku.edu> Thu.
Thu.
11:00–12:00
15:00–17:00
in 3029 Eaton

Undergraduate Supplemental Instructors and Office Hours

Danielle Fuller <dnfuller@ku.edu> Tue.
Wed.
14:00–15:00
14:30–15:30
Kelly Rodriguez <kellrodriguez@ku.edu> Thu. 14:30–16:30
in 2027 Eaton

Course Information

Schedule and Topics

This table will be filled in as the semester progresses. Note that additional information about each homework assignment is located on the 140 wiki, as linked by each assignment number in the table.

Note: this table has not yet been fully updated to this year

EECS 140 and 141 Fall 2010 Tentative Schedule
Date Lecture Reading Homework
Subject Key Concepts Required
 140 & 141 
 Optional 140 
 Required 141 
  #   Problems Due
 19 – 
 24 Aug. 
Administrivia
and Ethics
24 Aug.  Design Concepts design process
 binary numbers 
conversion
 BV: 1 01 handout  31 Aug. 
26 Aug.  Introduction to
Logic Circuits
variables & logic functions
switches
inversion
truth tables
logic gates & networks
 BV: 2.1–2.4 
 DB: 08, 11, 32, 04 
02  2.2, 2.5, 2.8, 
 2.13, 2.14, 
 2.19, 2.21, 2.31 
  – 
 EECS141 only
 2.35 
 puzzler 2 
 09 Sep. 
31 Aug.  Boolean algebra
Venn diagrams
 BV:2.5
02 Sep.  synthesis
SOP, minterms
POS, maxterms
 BV:2.6
04 Sep.  NAND and NOR gates  BV: 2.7 
 DB: 00, 02, 20, 51 
03  2.37, 2.38, 2.39, 
 2.45, 2.47 
 Quartus II 
  – 
 EECS141 only
 2.41 
 puzzler 3 
 14 Sep. 
09 Sep.  multiplexors  BV: 2.8 
14 Sep.  CAD tools  BV: 2.9  04  3.1, 3.2, 3.4, 
 3.5, 3.6 
  – 
 EECS141 only
 3.7, 3.9, 3.10 
 puzzler 4 
 21 Sep. 
16 Sep.  Implementation
Technology
transistor switches
NMOS gates
CMOS gates
 BV: 3.1–3.3 
21 Sep.  negative logic
standard chips
 BV: 3.3–3.5  05  3.36, 3.42 
 use Fig. 3.27 
 instead of 3.66 
  – 
 EECS141 only
 puzzler 5 
 28 Sep. 
23 Sep.  programmable logic
PLAs and PALs
CPLDs
 BV: 3.6–3.6.4 
28 Sep.  VHDL introduction
review for exam 1
 BV: 2.10–2.11 
30 Sep.  Exam 1: Chapters 1–2
05 Oct.  programmable logic
FPGAs
standard cells
gate arrays
 BV: 3.6.5–3.7  06  3.44, 3.46, 3.48, 
 3.49, 3.50, 
 3.51 (do timing simulation) 
 – 
 EECS141 only
 3.36, 3.38, 3.42 
 using Fig. 3.66 and 3.65 
 puzzler 6 
 12 Oct. 
07 Oct.  propagation delay
power dissipation
fan-in and fan-out
buffers
tri-state buffers
transmission gates
XOR gates
 BV: 3.8.5–3.9, 3.11 
 DB: 34, 125, 126, 86 
 BV: 3.8.1–3.8.4, 3.10
 
12 Oct.  Optimized
Implementation
of
Logic Functions
Karnaugh maps:
SOP
prime implicants
cover, cost
 BV: 4.1–4.2
14 Oct.  fall break: no class
19 Oct.  Karnaugh maps:
strategy
POS, don't care
multiple outputs
 BV: 4.2–4.5 07  4.1, 4.3, 4.4, 4.6
 4.16, 4.17, 4.18, 4.19
 – 
 EECS141 only
 4.10, 4.20 
 puzzler 7 
 26 Oct. 
21 Oct.  multilevel synthesis
review for exam 2
 BV: 4.6, 4.12–4.13  BV: 4.7, 4.8
26 Oct.  Exam 2: Chapters 3–4         
28 Oct.  Number
Representation
and
Arithmetic Circuits
binary representation:
unsigned integers
signed-magnitude
half adders
full adders: ripple carry
 BV: 5.1–5.2     08  5.1, 5.4, 5.5,
 5.6, 5.7
 5.13, 5.14
 – 
 EECS141 only
 5.8, 5.15 
 puzzler 8 
 09 Nov. 
02 Nov.  binary representation:
one's complement
two's complement
addition and subtraction
 BV: 5.3   
04 Nov.  fast adders
comparators
VHDL design
 BV: 5.4–5.5 
 DB: 182, 283, 85, 181 
 BV: 5.6
09 Nov.  binary representation:
floating point
BCD
ASCII
 BV: 5.7–5.9     09  5.25, 5.26, 5.27
 6.1, 6.4, 6.13
 6.23, 6.30, 6.35
 – 
 EECS141 only:
 5.15, 5.28
 6.7, 6.9
 puzzler 9 
 16 Nov. 
 Combinational-Circuit 
Building Blocks
multiplexors  BV: 6.1–6.1.1
 DB: 157, 153
 BV: 6.1.2
11 Nov.  decoders and encoders
demultiplexors
code converters
comparators
Exam 3 review
 BV: 6.2–6.7
 DB: 139, 138, 154, 
         148, 247, 85 
16 Nov.  Exam 3: Chapters 5–6
18 Nov.  Flip-Flops,
Registers, Counters,
and a
Simple Processor
latches
gated SR and D latches
setup and hold time
flip-flops:
master-slave
edge-triggered
 BV: 7.1–7.4
 DB: 279, 74, 73 
10  7.1, 7.3, 7.5, 7.8
 7.13, 7.17
 – 
 EECS141 only:
 7.33 7.34
 puzzler 10 
 30 Nov. 
23 Nov.  flip-flops:
preset and clear
JK and T
registers
shift registers
counters:
asynchronous
synchronous
 BV: 7.5–7.13, 7.16 
 DB: 164, 166, 93, 90 
 BV: 7.14–7.15
25 Nov.  Thanksgiving break: no class
30 Nov.  Synchronous
Sequential Circuits
state machines:
Moore machines
diagrams and tables
state assignment
 BV:8.1–8.2 11  8.3, 8.9, 8.20, 8.23
 – 
 EECS141 only:
 8.19, 8.24, 8.40
 puzzler 11 
 07 Dec. 
02 Dec.  Mealy machines  BV: 8.3–8.4
07 Dec.  adder example
counter example
 BV: 8.5, 8.7, 8.12  BV: 8.6, 8.8–8.12
09 Dec.  Asynchronous
Sequential Circuits
overview  BV: 9.1  BV: 9.2–9.3 12  optional
 9.1, 9.2
Digital System
Design
CPU building blocks  BV: 10.1  BV: 10.2
13 Dec.  Optional final exam review:
14:00–15:00 in Eaton 2010
14 Dec. 
Tue. 
Final Exam: Chapters 7–10 and comprehensive
10:30–13:00
30 Dec.  Final Grades Available

Entries in the Reading column are chapters and sections.

BV = Brown and Vranesic, Fundamentals of Digital Logic with VHDL Design
VHDL = Ashenden, Student's Guide to VHDL
DB = TI, Digital Logic Pocket Data Book (numbers refer to the circuit numbers at the top of the pages)


Exams

Exam 1

Exam 2 (midterm)

Exam 3

Final Exam 3

Note: while the final exam will concentrate on Chap 7–8, there will be a number of questions that cover Chap. 1–6; therefore students are strongly recommended to review all course material and study guides.

Exam Results

See the main course page for futher details on grading.

EECS 140/141 Fall 2010 Exam Results
Exam Statistics Distribution
 Min   Med   Max   Mean   Std Dev   0–49   50–54   55–59   60–64   65–69   70–74   75–79   80–84   85–89   90–94   95–100 
 Exam 1  37  83  97  74.5  22.5 
 Midterm 2  73  98  67.2  23.6 
 Exam 3  19  84  98  78.9  17.7 
 Final                                 

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©2006–2010 James P.G. Sterbenz <jpgs@eecs.ku.edu>