EECS 312 – Homework Assignments (Fall 05)

 

 

 

Listed below are the homework assignments for EECS 312, Fall 2005.  The dates are the due date for each assignment, which must be submitted before the beginning of class (see course homework policy).

 

Standard problem numbers (e.g., 2-5, 4-12) are problems from your textbook.  Special problems (e.g., SP2-5.3, or SP6-4.2) are old EECS 312 exam problems.  You get these problems by simply clicking on problem number below; it will link to a pdf file with the problem description.  If no homework is due that day, then “none” will be written next to the date.

 

Note: PLEASE submit you homework using the format as described in the homework policy (i.e., folded with the back page on the outside, the fold at the left, with your name, homework number, and course (EECS 312) all legibly written.

 

Home

 

Due Date           

 

Aug 19      none              

 

Aug 22      none

Aug 24      #1: SP1            

Aug 26      none        

 

Aug 29      #2: 3.2(a,b,c,d) Note:  The 4 circuits for this problem are shown in figure P3.2, found at the very top of page 219.           

Aug 31      #3:  SP 3.1-7, SP 3.1-8, SP 3.1-9, SP 3.1-10, SP 3.1-12  Make sure you explicitly show all the steps in your circuit analysis, including what you ASSUMED, what you ENFORCED, each step of you ANALYIS, and what you CHECKED (e.g., iD =2.3 mA > 2 a)!!!!!!!!        

Sep 2        #4: 3.18, 3.19, 3.22(b), SP 3.2-1, SP 3.2-2, SP 3.2-5, SP 3.2-7          

 

 

Sep 5        Labor Day

Sep 7        #5: 3.46, 3.48, SP 3.3-7, SP 3.3-13  

Sep 9        #6: 3.37,  SP 3.3-1, SP 3.3-5, SP 3.3-11, SP 3.3-12       

 

Sep 12      #7: SP 3.3-4, SP 3.3-15           

Sep 14      none        

Sep 16      #8: SP 3.3-3, SP 3.3-6, SP 3.3-9, SP 3.3-10, SP 3.3-14, SP 3.3-17           

 

Sep 19      #9: SP 3.4-4, SP 3.4-5, SP 3.4-7, SP 3.4-9

Sep 21      none        

Sep 23      Exam I            

 

Sep 26      #10: 3.66(shunt resistor R is 82 W), SP 3.4-1, SP 3.4-3, SP 3.4-10

Sep 28      none

Sep 30      #11: SP 3.5-4, SP 3.5-5, SP 3.5-7, SP 3.5-8

                 

Oct 3        #12: SP 3.5-6          

Oct 5        none        

Oct 7        #13: SP 3.5-1, SP 3.5-2

 

Oct 10      #14: SP 3.6-1, SP 3.6-2, SP 3.6-3, SP 3.6-4

Oct 12      #15: SP 3.7-1, SP 3.7-2, SP 3.7-3, SP 3.7-4               

Oct 14      Fall Break

 

Oct 17      none        

Oct 19      none        

Oct 21      #16: 4.11, 4.12, 4.13, 4.17(a), 4.19, 4.24, 4.26            

 

Oct 24      #17: 4.30, SP 4.2-1          

Oct 26      none        

Oct 28      Exam II         

 

Oct 31      #18: 4.42(a), 4.43(g), SP 4.3-1, SP 4.3-8, SP 4.3-10

Nov 2       #19: 4.37, SP 4.3-2, SP 4.3-6, SP 4.3-9    

Nov 4       #20: SP 4.6-1, SP 4.6-2, SP 4.6-4 (Note I have deleted SP 4.6-3)

 

Nov 7       #21: 1.82, SP 1.7-1, SP 1.7-2    

Nov 9       none        

Nov 11      #22: 4.105(b,c), 4.111, SP 4.10-1, SP 4.10-3,  SP 4.10-4,  SP 4.10-5    

 

Nov 14      #23: SP 4.11-1, SP 4.11-2, SP 4.11-3, SP 4.11-4

Nov 16      #24: 10.321, SP 10.3-1, SP 10.3-2, SP 10.3-3             

Nov 18      #25: 10.46

                Note 1:  Make 2 gates, one for output S and the other for output C0.

 

Nov 21      #26: 11.181, 11.21, 11.342, 11.37        

Nov 23     Thanksgiving Break

Nov 25     Thanksgiving Break

Note 1:  A “square array” is one where the  number of rows equals the number of columns.  Make sure you determine the number of address bits for both the row and column decoder of the reconfigured  array (i.e., the array with 16 columns).

Note 2:  Assume the NOR decoder is made using pseudo-NMOS technology.

 

Nov 28     none        

Nov 30     Study for exam III        

Dec 2       Exam III         

 

Dec 5       #27: SP 5.4-1, SP 5.4-2, SP 5.4-5    

Dec 7       #28: SP 5.4-3, SP 5.4-4, SP 5.4-6    

Dec 9       Stop Day