Field programmable gate arrays (FPGA) and monolithic DSP microprocessors are powerful technologies which can be used to maximum advantage in military software radio and radar processing applications. The objective of our research is to create a set of tools and technologies that enable the rapid design and implementation of radio processing functions and synthetic aperture radar (SAR) processing functions in FPGA based systems in a reliable and trustworthy manner. Our research effort is composed of three tasks:
The first task is aimed at creating a set of tools and an environment supporting signal processing applications:
(a) within a high level language,
(b) on a wide range of FPGA architectures,
(c) in a reliable and robust manner, and
(d) suitable for dynamic and flexible execution management.
The second task has two aspects:
(a) radio communications processing is an extremely important defense application area and
(b) the application is challenging and will ensure the FPE has sufficient capabilities for important applications. Likewise, the third task is an important defense application and will be a significant test of the FPE. In particular, SAR processing requires large random access memories to hold signal values and accesses to that memory are data dependent, i.e. the addresses depend on values in the data stream (e.g. platform position). The motivation for our proposed work is the design and implementation of high performance radio communications systems. When digital signal processing at wide bandwidths is required the radio designer turns to specialized hardware which can operate at much higher throughputs than is possible with a conventional or specialized DSP microprocessor. These specialized alternatives include application specific standard products (ASSP), application specific integrated circuits (ASIC), and field programmable gate arrays (FPGA). Application Specific Standard Products (ASSP) such as FIR filters, correlators, and FFT processors, permit certain popular DSP algorithms or functions to be optimized in hardware at the cost of flexibility. Use of ASSPs can significantly increase the device count, often presents special interface problems which can lead to further complications, and the interconnections are fixed at design time.. Furthermore, due to a narrow range of applicability and delays from concept to manufacturing, many ASSPs may not be available in state of the art process technology [1]. When performance is a factor and product volume is high, many designers turn to ASIC technology. ASIC technology offers the ability to design a custom architecture that is optimized for a particular application. For example, a conventional DSP microprocessor has only a single multiply-accumulate (MAC) stage, so each filter tap must be executed sequentially at the base clock frequency. An ASIC implementation of a DSP algorithm, on the other hand, might have multiple parallel multiply-accumulate (MAC) stages enabling multiple operations per clock cycle. While offering the possibility of higher processing bandwidths, ASICs have a significant delay between concept and implementation due to significant design and manufacturing times. When comparing the performance of the ASIC versus the DSP microprocessor it becomes apparent that the DSP microprocessor offers slow speed but maximum flexibility (due to programmability) while the ASIC provides high speed with minimal flexibility. Between these two extremes lies the Field Programmable Gate Array (FPGA) [2]. Modern FPGAs can implement functions beyond the capabilities of today's DSP microprocessors. In fact, they have the potential to provide performance increases of an order of magnitude or better over traditional DSP microprocessors, but with the same flexibility [3]. These devices can provide the programmability of software, the high speed of hardware and can be re-configured in-circuit with no physical change to the hardware. In fact, FPGAs are really "soft" hardware, in that they are a good compromise between flexible all-software approaches which unfortunately limit throughput, and custom hardware implementations, which are more expensive and inflexible [4] FPGAs offer a powerful approach - an architecture tailored to the specific application. Because the logic in an FPGA is flexible and amorphous, a DSP function can be mapped directly to the resources available on the device. Modern FPGAs have sufficient capacity to fit multiple MACs or algorithms into a single device along with the interface circuitry required by the application - a single chip solution. The objective of implementing significant DSP algorithms in FPGAs presents several technical challenges. Among the important challenges are: o What language should be used to describe the DSP algorithm? o How can one reliably re-use parts of different existing designs/algorithms in a new design/implementation? o How can one reliably transform (or compile) a DSP algorithm from its description to an implementation? o How can one reliably transform a DSP algorithm under different performance criteria, such as power, speed, size, and precision? o How can one reliably transform a DSP algorithm for implementation on different FPGA architectures and systems? We believe a functional programming language [9] and environment is best suited to meeting these technical challenges. The next section describes our proposed Functional Programming Environment. Following that we show how the tools are applied to radio communications and SAR processing functions.
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