Jayhawk

University of Kansas

DSP on FPGAs

 Circuit

DSP on FPGA Papers from KU

  • Automatic Implementation of FIR Filters on Field Programmable Gate Arrays
    Satish Mohanakrishnan and Joseph B. Evans
    IEEE Signal Processing Letters, March 1995.
    PostScript, PDF

  • Efficient FIR Filter Architectures Suitable for FPGA Implementation
    Joseph B. Evans
    IEEE Trans. Circuits & Systems, July 1994.
    PostScript, PDF

  • FPGA Implementation of Digital Filters
    Chi-Jui Chou, Satish Mohanakrishnan, and Joseph B. Evans
    Proc. 1993 Int. Conf. Signal Proc. Appl. & Tech.
    PostScript, PDF

  • An Efficient FIR Filter Architecture
    Joseph B. Evans
    Proc. 1993 IEEE Int. Symp. Circuits & Systems.
    PostScript, PDF

  • A Framework for the Design of High Speed FIR Filters on FPGAs
    Satish Mohanakrishnan and Joseph B. Evans
    Proc. 1994 Int. Conf. Signal Proc. Appl. & Tech.
    PostScript, PDF

  • An Efficient Bit-Serial FIR Filter Architecture
    Yong Ching Lim, Joseph B. Evans, Bede Liu
    Circuits, Systems, and Signal Processing, May 1995.
    PostScript, PDF

    • Other FPGA Information

  • The FPGA Page

    • This work was supported by the KTEC Center for Excellence in Computer-Aided Systems Engineering, now the Information & Telecommunication Technology Center.

    Send any comments to Joseph B. Evans, evans@ittc.ku.edu.
    Last updated: 18 September 1997.